Minimum current requirement for external VREF+ on STM32G474

[nbsown]

Hi ST Community,

I'm using an external precision voltage reference connected to the VREF+ pin of the STM32G474.

I would like to know:

• What is the minimum output current capability required for the external VREF source?
• Is there any specification for the average or peak current drawn from the VREF+ pin during ADC conversions?
• Does the required current depend on the ADC sampling rate, the number of ADCs operating simultaneously, or the sampling time?
• I couldn't find a clear specification for the VREF+ input current in the datasheet or reference manual.

Any explanation or recommendation would be greatly appreciated.

Thank you!

[Andrew Neil]

Does this answer your question?

https://www.st.com/resource/en/datasheet/stm32g474re.pdf#page=139

via: https://www.st.com/en/microcontrollers-microprocessors/stm32g474re.html

[nbsown]

Oh, it looks like I missed it. Thank you very much!

[MasterT]

Q: 

• Does the required current depend on the ADC sampling rate, the number of ADCs operating simultaneously, or the sampling time?

Since architecture is SAR, and there are no pre-charge buffers on signal inputs and on reference inputs, than rough approximation is that I-ref = I-inputs. And I-inputs = V / R, where R = 1/ 2*PI()*Freq*C, C - sampling and hold, Freq - sampling rate. Sure, multiply by N if more than 1 ADC operating.

[nbsown]

Thank you very much!

[Johnsmiteo]

That's a great question. I'm particularly interested in whether the VREF+ current requirements scale noticeably when multiple ADCs are operating simultaneously or at higher sampling rates. It would also be helpful if there were clearer guidance on the transient current demands during conversions so designers can choose an appropriate precision reference with enough headroom.

[tomcarry0]

This is a really useful question. When selecting an external reference, understanding both the average and transient current requirements is important for maintaining ADC accuracy. I'd also be interested in knowing whether simultaneous conversions across multiple ADCs significantly affect the instantaneous current demand on VREF+, as that could influence the amount of decoupling and headroom designers should plan for.