intra-bank Flash write/erase behavior on STM32L071 (dual-bank Flash)

[TKopp.67]

Dear ST Support Team,

I am developing a custom bootloader for the STM32L071CBY6TR (128 Kbyte, dual-bank Flash) and I have a question regarding the exact behavior of the Flash controller that I could not fully clarify from RM0367.

Context:
- My bootloader occupies the first 32 Kbytes (0x08000000 - 0x08007FFF), entirely within Bank 1.
- My application occupies 96 Kbytes starting at 0x08008000, which means it spans across the Bank1/Bank2 boundary at 0x08010000: the last 32 Kbytes of Bank 1, and roughly 64 Kbytes of Bank 2.

RM0367 states that read operations from one bank can be performed while write or erase operations are performed on the other bank (cross-bank read-while-write). However, I could not find documentation describing the behavior when a write/erase operation is performed on one bank while code execution (instruction fetch) continues from a *different page within the same bank* — which is exactly my bootloader's situation when it needs to erase/program the tail portion of Bank 1 that holds part of the application, while the bootloader code itself keeps running from the beginning of that same bank.

My specific questions are:

1. When erasing/programming a page in Bank 1, does the CPU stall (wait state) if it tries to fetch an instruction from a different, non-erased page within the same Bank 1 — similar to the documented single-bank stall behavior — or is this operation simply not permitted/undefined?

2. Is there an application note (e.g., an IAP/bootloader-specific AN) that documents this intra-bank scenario explicitly for the STM32L071/L072/L073 devices?

Thank you very much for your clarification.

Best regards,
Thomas Kopp

[T_Hamdi]

Hello ​@TKopp.67 ,

 

1. When erasing/programming a page in Bank 1, does the CPU stall (wait state) if it tries to fetch an instruction from a different, non-erased page within the same Bank 1 — similar to the documented single-bank stall behavior — or is this operation simply not permitted/undefined?

According to your question and the reference manual, the answer is described in Section 3.3.3, "Reading the NVM."

From this, we understand that the only possible use case with two banks is to perform read operations on one bank while write or erase operations are carried out on the other bank. In your case, it is not possible to do both operations on the same bank at the same time.
Therefore, as a solution, we recommend placing your application code in the second bank. Also, why did you choose this application code partitioning between the two banks?

Best regards,

Hamdi

 

 

[Nathri]

Try moving your erase/program routine to RAM. 

Running from RAM avoids the two-Flash-operations issue entirely.

**********

For IAR/Keil use __ramfunc,

for GCC use __attribute__((section(".ramfunc"))).

**********

Saw this workaround on STM32C0 too. Just an option if you need it.