STM32 MCUs

Hi all,disclaimer: I used AI to translate my question to english:I'm designing the power supply for a solar-charged, battery-powered outdoor device (wildlife camera controller) built around an STM32L476VG. I'd appreciate a sanity check of the architecture and the regulator choices.System:Input: 2S Li-Ion (NP-F pack), 6.0–8.4 V, reverse protection via P-FET MCU in STOP2 most of the time (target sleep budget: < 10 µA for the whole board) Always-on: MCU, RTC (AB1805), I2C EEPROM, a µA-class wake-up receiver Switched loads (active phases only, seconds to minutes): LoRa module (TX approx 120 mA), SD card (write bursts approx 100 mA), OLED, GPS Separate 5 V rail (TPS62147, EN-gated) for a Raspberry Pi that wakes for uploadsCurrent design: one 3.3 V rail from an MCP1703A (2 µA IQ, 250 mA), all loads behind individual load switches (TPS22919 etc.).Concern: worst-case concurrency (LoRa TX + SD write + MCU + OLED) sums to approx 250 mA -right at the LDO's limit, and (8.4 − 3.3 V) × 0.25 A app

The errata sheet for the STM32U585 (ES0499) is no longer listed in the documentation section on the product page, and the old download link now returns a 404 error. For reference, the following post includes a download link for ES0499 that no longer works. https://www.st.com/resource/en/errata_sheet/es0499-stm32u575xx-and-stm32u585xx-device-errata-stmicroelectronics.pdf How can this document be retrieved?  Thanks,Owen

Are there any single MCU + LoRa 2.4 GHz ICs in the world?

I used STM32F103 in a mix configuration of bare-metal&HAL supplied by STM32CubeMX. I'm not sure ST can provide the documentation that can be referenced to generate the SBOM for cybersecurity purpose. Is there any recommended tool to scan the firmware project folder. If ST is yet to provide a way to auto-generate SBOM for cybersecurity requirement, possible to use manually curated SPDX-based JSON format for machine processing. If anyone had gone through similar process for regulatory review, can you please share the experience? Any inputs/advise would be greatly appreciated. Thank you.

Hello, we are testing using an STM32H7R7L8H6 paired with an IS42S32800L-6BL. There are no data failures at 100MHz, but data failures occur after prolonged execution at 150MHz. What is the maximum FMC execution speed of the STM32H7R7L8H6? This test was conducted with the MCU DVDD pin unconnected. Is this related to the DVDD pin connection?

Hello,I am debugging USB function on STM NUCLEO-H723ZG demo board. I set the USB_DEVICE Mode as CDC(Virtual Port) mode. USB_OTG_HS can as below.Now I can get the virtual port number on the computer. But the VBUS over current LED (LD7) is always on. It indicates the VBUS over current. But I have configured the EN pin of STMPS2141STR as high (Set PD10/USB_FS_PWR_EN) to disable this fault. Can anyone please help to check what’s the problem? Thanks, 

Setup  - MCU: STM32U595VITxQ (Cortex-M33)  - ADC: ADC4, 57Mhz，12-bit, 7 channels, 6400 Hz sample rate, triggered by TIM1  - Data path: GPDMA1 in linked-list circular mode, double-buffered with half/complete callbacks (128 samples per half-buffer). DMA writes directly into a static INT16U s_adc4_result[256][7] buffer in normal SRAM.  - Signal chain: external current/voltage sensors → signal conditioning board (op-amps, anti-alias filter, DC bias) → ADC4 input pins  - Firmware: FreeRTOS, half-callback copies 128 samples per channel into a ring buffer (PF_TOTAL_WAVE_NUM = 40 slots × 128 samples), pf_task consumes from queue  Symptom  Most of time, everything works fine. But some times something wrong happened，in a log file we captured, channels simultaneously read byte-identical constant values.Questions:  1. Has anyone seen an STM32U5 ADC report "healthy" (no OVR, no error, ADSTART set) while consistently delivering a constant code per channel? Are there silicon errata I should check?  2

I spent a lot of time designing a prototype using the STM32H573MIY3Q, but now it’s out of stock (DigiKey/Mouser/JLC) and 78 week lead time (available Jan 1, 2028). I’m kicking myself for not asking earlier about STM’s commitment to this part.How do we get samples now? I guess I can go to the scalpers...But then is it even smart to design this into a product? What is STM’s planned production ramp?Initially I’ll sell a few hundred units but if it goes well I might need 10K+ per year.Am I delusional in hoping for the possibility?I apologize for my tone of frustration, but SEVENTY EIGHT WEEK lead time is hard to believe, and upsetting. Is this not a flagship microcontroller (STM32H5) and flagship package (WLCSP-80)?

Hi everyone,I'm working with the STM32F446RE and exploring the 6-step BLDC motor control example provided by the STM32 Motor Control SDK. In the CubeMX configuration of the firmware:3 GPIOs are configured as analog inputs:M1_BEMF_U → PC3 → ADC1_IN13M1_BEMF_V → PA7 → ADC1_IN7M1_BEMF_W → PB0 → ADC1_IN8However, in the ADC Injected Conversion Mode, only Channel 13 (PC3) is selected and used (1 injected conversion configured).See image below for reference:My question is:Why are all 3 BEMF pins configured in CubeMX if only Channel 13 is used in the ADC injected group?I expected that all 3 channels would be used in the injected sequence to sample U, V, and W BEMF voltages.Do they dynamically change the injected channel in code depending on the commutation step? Or is there another reason for this configuration?Thanks in advance for any clarification!

Hi everyone,I'm designing a custom development board based on the STM32H750XBH6 and originally planned to use the ISSI IS42S32400F-6BL (128 Mbit, 4M × 32, SDR SDRAM, 166 MHz, 90-ball BGA).However, this part appears to be obsolete/end-of-life, and availability is becoming an issue.I'm looking for recommendations for a newer SDRAM that is:Fully compatible (or requires minimal hardware/software changes) 128 Mbit or larger 32-bit data bus 3.3 V SDR SDRAM 166 MHz (or higher) 90-ball BGA (preferred) Currently in production and readily available from major distributorsHas anyone recently designed an STM32H750/H743 board and selected a newer SDRAM instead of the IS42S32400F-6BL?I'd appreciate recommendations for specific part numbers that are currently in production and known to work well with the STM32 FMC interface.Thanks in advance!

Hi everyone,I'm working on an STM32H743-based product that already has a custom bootloader and I'm looking for the best industry practice for implementing a bootloader fallback mechanism.Current architecture0x08000000 Primary Bootloader0x08020000 Factory Application0x08080000 Default ApplicationThe bootloader already performs:Application validity checks (MSP and Reset Handler) CRC verification of the Factory and Default applications UART firmware update Automatic fallback from Default Application to Factory ApplicationThe applications are working as expected.New requirementThe new requirement is that if the primary bootloader becomes corrupted, the system should be able to boot from a backup bootloader stored elsewhere in flash, without requiring physical access (the device is remotely deployed).I understand that after reset the Cortex-M7 hardware simply does:MSP = *(0x08000000)PC = *(0x08000004)and immediately jumps to the Reset_Handler.My understanding is:If the vector table or R

Hello,At present I trt o interface an SPI based SSD1309 Display and I2C based DS3231 RTC with STM32F103RBT6 using Nucleo board MB1136 F103RB C. For your reference I have attached screenshot of port assignment for those devices.  void Init_GPIOs(void) {/* --- 1. Peripheral Clock Enable --- */// Enable clocks for all GPIO ports and AFIO (Alternate Function I/O)RCC->APB2ENR |= (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN |RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN |RCC_APB2ENR_AFIOEN); /* --- 2. Pin Remapping & JTAG Management --- */// Disable JTAG/SWD remap to reclaim PB3, PB4, and PA15 for GPIO/Alternate Function usageAFIO->MAPR &= ~AFIO_MAPR_SWJ_CFG;AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_JTAGDISABLE;// Remap SPI1 to PB3/PB4/PB5 as per hardware designAFIO->MAPR |= AFIO_MAPR_SPI1_REMAP; /* --- 3. Initialize Display Control Pins (Soft-Step) --- */// Configuring critical control pins first ensures the display state is stable// before the high-speed SPI clock begins toggling.GPIOB-&gt

Dear STM32 Technical Team:Our original design is implemented on the STM32F407, utilizing a single ADC pin for analog signal acquisition. Upon detection of a key trigger signal, high-speed data acquisition is performed via TIM1-triggered ADC1 with DMA transmission, where Analog Watchdog 1 is configured with Threshold A for boundary supervision. In the idle state without a key trigger, TIM2-triggered ADC2 operates in background mode with Analog Watchdog 2 (Threshold B) to continuously monitor abnormal signal fluctuations in real time.Due to the limited on-chip RAM of the STM32F407, we have migrated the firmware to the STM32L4S5 microcontroller. However, this device only features a single ADC peripheral, which prevents the independent dual-ADC operation implemented in the original design. Furthermore, although the STM32L4S5 integrates three analog watchdogs, the hardware does not support configuration of independent threshold levels for separate operational modes.We kindly request your of

TouchGFX version 4.25.0 CubeMX version 6.17.4*  STMCubeIDE version 2.0.0*edited versionI created a development environment starting with TouchGFX and used Generate Under Root in CubeMX.  This did a great job of setting up the directory structure without links so that it is easier to navigate in the STM32CubeIDE application.Part of this process automagically moves the middleware and driver directories from the STM32CubeIDE directory to the root directory.When the .project file is created by the TouchGFX code generation it handles the movement of all these files and include directories like a champ, except the Properties=>C/C++ Build=>Settings=>MCU/MPU G++ Linker=>Libraries=>Library search path for the libtouchgfx-float-abi-hard.a library.It sets the path to "${workspace_loc:/STMCubeIDE/Middlewares/ST/touchgfx/lib/core/cortex_m7/gcc}" instead of "${workspace_loc:/${ProjName}/Middlewares/ST/touchgfx/lib/core/cortex_m7/gcc}"It's a quick fix to edit it to

Hi,I'm developing a composite USB device on STM32N6 with:- 2x CDC ACM interfaces (Dual Virtual COM Port)- 1x UVC (USB Video Class) interface for camera streamingThe CDC ports work correctly. The UVC class enumerates successfully and the camera application opens without errors. However, the video stream shows a black screen - no actual frame datais being transmitted. What Works1. USB Composite device enumeration succeeds2. Both CDC ACM ports work (LOG port sends heartbeat, DATA port echoes)3. UVC class registers correctly with USBX4. Host can open camera application (VLC, Cheese, etc.)5. UVC GET_DEF(PROBE) requests are handled correctly6. SET_CUR(PROBE/COMMIT) requests are handled correctly7. StreamChange callback fires when host starts streaming (alt=1)8. Packets are queued via ux_device_class_video_write_payload_get() (returns success)9. ux_device_class_video_transmission_start() returns UX_SUCCESSWhat Doesn't Work→ PayloadDone callback is never triggered→ No video data reaches the ho

Dear,Is it possible for execution within HDPL_x to use SAES (Secure AES) with a DHUK (Derived Hardware Unique Key) from HDPL_y where x > y?For example:Execution within HDPL2 makes use of SAES to encrypt plaintext p using its DHUK, this results in ciphertext cAfterwards, upon reset, execution within HDPL1 needs to be able to read plaintext p (e.g., by decrypting the stored ciphertext c using HDPL2's DHUK) without changing the HDPL.Is this possible with SAES, and if yes, how?Thanks a lot!

 I’m trying to use the FMC and SDRAM (IS42S16400J) to expand the H7’s running memory. I have the FMC configured in SystemInit and the linker setup to put all readwrite into SDRAM. I’ve verified that I can create variables normally, they’re placed in SDRAM, and can be read and manipulated normally.Now that I have minimal functionality, I’m starting to add more peripherals and functionality.int main(void){ /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_SDMMC2_SD_Init(); MX_USB_OTG_HS_PCD_Init(); MX_FATFS_Init(); /* USER CODE BEGIN 2 */ MX_USB_DEVICE_Init(); /* USER CODE END 2 *

Hi,after starting with Nucleo-L432KC development board I need to switch to a variant with more I/Os, and thus I’m creating a stand-alone development board with STM32L462CET in LQFP48 package.I purchased a STLink-V3MINIE for programming/debugging but, like others, was confused on how to properly connect the STLink to the MCU. Since various answers are given in lots of threads I summarized in a simplified sketch what I consider as correct.Please have a look on attached schematic and configuration of MCU done in CubeMX. To keep it as simple as possible I removed everything but the MCU, the STDC14 connector of the V3MINIE and just an LED to apply the minimum blink-example.Please, focus on the connection of STDC14 connector and BOOT0. I think, with this, it is possible to download the blink-software and run the debugger. Am I correct?RegardsSebastian 

Hi everyone,I am working with the STM32C071 and experiencing problems with USB enumeration after my bootloader execution.I wrote a custom bootloader that performs checks (like CRC, metadata, etc.) and can also trigger the embedded STM32 DFU bootloader in System Memory using this method:void boot_jump_to_bootloader(void){ uint32_t i = 0; void (*SysMemBootJump)(void); uint32_t BootAddrC0 = 0x1FFF0000; __disable_irq(); SysTick->CTRL = 0; HAL_RCC_DeInit(); for (i = 0; i < 8; i++) { if (i < (sizeof(NVIC->ICER) / sizeof(NVIC->ICER[0]))) { NVIC->ICER[i] = 0xFFFFFFFF; NVIC->ICPR[i] = 0xFFFFFFFF; } } __enable_irq(); SysMemBootJump = (void (*)(void)) (*((uint32_t*) ((BootAddrC0 + 4)))); __set_MSP(*(uint32_t*) BootAddrC0); SysMemBootJump(); while (1) { /* Code should never reach this loop */ }}After performing my bootloader-specific instructions, I jump to the main firmware application using this f

There seems to be a recurring error in the HAL documentation (e.g. UM2570, but also in others  STM32L5?) UM2570 - Rev 2 page 60/2926The description of the flag does not match the flag nameHAL_FDCAN_ERROR_FIFO_EMPTYPut element in full FIFOHAL_FDCAN_ERROR_FIFO_FULLGet element from empty FIFO 

Hi Everybody,I posted a comment here https://community.st.com/t5/stm32-online-courses/stm32h5-secure-manager-course/bc-p/824487/highlight/true#M27 yesterday because I am trying following the online course and what is written in the wiki to start developing an application on the STM32H573VI using the secure manager.At the moment I am starting the development by using the nucleo board for H573 however, by following the wiki, the only project that could be used for deploying the solution is an handswritten example that does not use the CubeMx.If I try to follow the old documentation on the youtube videos, as explained in the link provided, I am unable to set the boot path correctly.At the moment I am a bit lost, should I build my project without the use of CubeMx in case of secure manager? Will it be added in the future? I am missing something straightforward? thank you in advanceAndrea

My MCU is STM32H753 on custom PCB. It is running at 480 Mhz. I use USB USB_OTG_FS it is clocked by RC48.On “Middleware and Software packs” I have enabled “FATFS”, “FREERTOS” and “USB_HOST”I generated project by using CubeMX 6.17 with “STM32Cube_FW_H7_V1.13.0”.For more details see attached pictures with configurations. I use FreeRTOS function uxTaskGetSystemState to get info about CPU time per task.In my project I have FatFS test module that performs some read write tests. When I check CPU usage I get this numbers for tasks: “fatfs_test” CPU: 43% “USBH_Queue” CPU: 46% left 11% are utilized by GUI.I ran tests with USB DMA enabled and disabled - there is no difference. So, the question is: Is it OK for “USBH_Queue” task to utilize that much CPU when read/write operations in progress??? For example I have similar test for SD-card, and I get this numbers for tasks: “fatfs_test” CPU: 51% “IDLE” CPU: 35% GUI and other tasks CPU: 14%USB OTG FS pinsUSB OTG FS parametersUSB OTG FS NVIC SettingsU

JW

While looking at STM32U3C5 and STM32H503 datasheets I found incorrect information on ICACHE. Quote:Hit ratio improved by two-ways set-associative architecture and pLRU-treplacement policy (pseudo-least-recently-used, based on binary tree), algorithmwith best complexity/performance balance The problem is: pseudoLRU may only be applied to 3- (or more) way set-associative caches. With 2-way set-associative, the single flip-flop per set provides true LRU and there is no such thing like “pseudoLRU” for 2 ways. You can’t do binary tree with a single flip-flop.  PseudoLRU is normally used with 4 or more ways, since for 4 ways pseudoLRU requires 3 flip-flops organized as 2-level tree, with simple state transition logic while true LRU - 4 flip-flops and 12 states with much more complex state transition logic.I suspect the same error might be present in all the STM32 documents describing MCU caches which are 2-way set-associative.

Hello,We are experiencing an intermittent CAN-FD issue in our system and would appreciate any advice from the community. We have developed seven new I/O modules based on the STM32G491VETx with an external 20 MHz crystal.All have the same CAN configuration using ISO1042BDWVR. The CANopenNode stack with the CANopenNodeSTM32 driver is implemented on all electronic units.See https://github.com/CANopenNode/CanOpenSTM32  The CAN bus operates at 250 and 500 kbit. All electronic units occasionally experience the problem that the NodeGuarding or heartbeat (set to 3s!!!) stops responding after 24 hours to 5 days. SDOs do not respond either, whilst TPDOs continue to operate. We have set up over 10 networks, each with 4 different nodes (all G491), and all exhibit the same behaviour sporadically. We can rule out hardware faults.The electronic runs for about 48 hours with no Problem on 500k an low bus load (about 2%, Nodeguarding and some TPDO/RPDO).Suddenly FIXFDCAN RF0 FIFO FULL and RX NEW MESSAGE