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Associate
July 31, 2026
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Trying to set the STM32c031 clock to 48MHz. Target is not responding, retrying...

  • July 31, 2026
  • 4 replies
  • 83 views

I have a STM32C031C6 and I’m trying to set the clock to be 48MHz

 

It works when I have the for loops in there, but its not supposed to have them and I want to get it working properly without needing them.

If I comment out 1 of the for loops, then after that it gives me this error 

I’m not sure what I am doing wrong, I think I’m not waiting properly for something, but I don’t know what that is.

Error in executing 'cont' command ...

Target is not responding, retrying...

Target is not responding, retrying...

Shutting down...

Target is not responding, retrying…

 

This is the code.

#include "stm32c031xx.h"

void speed_up_to_48mhz(void){


// 1. ENABLE HSI and wait for the HSI to become Ready
RCC->CR |= (1U << 8);

while (!(RCC->CR & (1U << 10)));


for(volatile int i =0; i<1000000; i++){}


//bit 8 is prefetch
//bit 9 is instruction cache


//1 wait state
FLASH->ACR = (1U << 9) | (1U << 0);

FLASH->ACR &=~ (1U << 8);

volatile uint32_t acr = FLASH->ACR;



//ahb prescalar
RCC->CFGR &=~ (1U << 11);
RCC->CFGR &=~ (1U << 10);
RCC->CFGR &=~ (1U << 9);
RCC->CFGR &=~ (1U << 8);


//apb prescalar

RCC->CFGR &=~ (1U << 14);
RCC->CFGR &=~ (1U << 13);
RCC->CFGR &=~ (1U << 12);


RCC->CR &=~ (1U<<11);
RCC->CR &=~ (1U<<12);
RCC->CR &=~ (1U<<13);


while (!(RCC->CR & (1U<<10)));



for(volatile int i =0; i<1000000; i++){}



}

 

Best answer by Carlo Ramirez

I’d check the clock source and PLL configuration first, especially the ready/status flags and the order in which you switch SYSCLK. The delay loops may be masking a timing or synchronization issue rather than actually fixing it. Also, make sure the FLASH wait-state configuration is applied before increasing the CPU clock. The exact point where execution stops would help narrow it down.

4 replies

Carlo RamirezBest answer
Associate
July 31, 2026

I’d check the clock source and PLL configuration first, especially the ready/status flags and the order in which you switch SYSCLK. The delay loops may be masking a timing or synchronization issue rather than actually fixing it. Also, make sure the FLASH wait-state configuration is applied before increasing the CPU clock. The exact point where execution stops would help narrow it down.

housemanAuthor
Associate
August 4, 2026

thanks, I needed to apply the flash wait state before increasing the clock.

 

 

Visitor II
July 31, 2026

Your clock source switch is missing. You enable HSI but never tell the MCU to actually use it.

After your FLASH ACR config, add:

********

RCC->CFGR = (RCC->CFGR & ~(0b11 << 0)) | (0b01 << 0);

while ((RCC->CFGR & (0b11 << 2)) != (0b01 << 2));

********

The SWS bits confirm the switch is done.

housemanAuthor
Associate
August 4, 2026

thanks, I needed to apply the flash wait state before increasing the clock.