CSI_PFCR.DLD bit description contradicts HAL implementation

[pyven-dr]

RM0486 describes CSI_PFCR bit 16 (DLD) as follows:

 

Bit 16 DLD: Data lane direction of lane 0
0: Rx
1: Tx

Per this description, configuring the CSI-2 host to receive from a camera sensor (i.e. lane 0 in RX mode) should require DLD = 0.

However, in the shipped HAL, HAL_DCMIPP_CSI_SetConfig() explicitly sets DLD = 1 (via CSI_PFCR_DLD) when configuring the PHY for CSI-2 RX capture from a camera sensor:

WRITE_REG(csi_instance->PFCR, (0x28U << CSI_PFCR_CCFR_Pos) |
(SNPS_Freqs[pCSI_Config->PHYBitrate].hsfreqrange << CSI_PFCR_HSFR_Pos) | CSI_PFCR_DLD);

The HAL source even contains a comment acknowledging the discrepancy:

/* set basedir_0 to RX DLD 0 RX, 1 TX. Synopsys 1 RX 0 TX  + freq range */

This strongly suggests that the underlying Synopsys D-PHY basedir signal has the opposite polarity (1 = Rx, 0 = Tx) from what's documented for the DLD bit in RM0486, and that the HAL was written/validated against the actual behavior rather than the RM's bit description.

Is this a mistake of myself or a real error in the RM/HAL ?

[FBL]

Hi ​@pyven-dr 

DLD bit in CSI_PFCR reflects the external sensor status from the STM32N6 point of view, not the STM32N6 host point of view.

• DLD = 1 means the external camera sensor is in TX (Transmit) mode.
• DLD = 0 means the sensor lanes are not actively transmitting HS data.

So, HAL is consistent with the intended meaning; the RM bit description should be clarified. An internal ticket CDM0064937 is submitted to dedicated team.

[pyven-dr]

Thank you for the clarification.