Is low impedance for the ADC input good or bad?

[Backflip]

I have noticed several recommendations on internet, that recommend providing a low high frequency impedance driving the ADC input for the MCU. For instance, you could add an RC-filter with the capacitance directly between the input pin and analog ground.

 

This is one of the recommendations:

https://community.st.com/stm32-mcus-products-25/many-people-have-complained-about-noise-on-adc-inputs-maybe-to-do-with-impedance-has-this-be-rectified-on-any-version-or-family-of-the-stm32-42573?tid=42573&fid=25

 

Well, I am not sure of such a recommendation anymore…

 

Perhaps I should just state that I am a novice regarding the use of STM32 processors, but I am old regarding general electronics design and electrical noise.

 

I have just tried this circuit with a Nucleo STM32G474RE board with 100 nF decoupling capacitor and a series resistor that I vary on the input pin:
 

 

The preconditions are that I make an AD-conversion every second and with a 170 MHz sysclock and a 42.5 MHz ADC clock. The sample time is set to 12.5 clock cycles or 294 ns. No oversampling.

 

With the R-resistor set to 0 ohm, I get a peak-peak variation in the result value over one minute of about 33 LSB. When I change the resistor to 6.8 kOhm, the variation drops to about 12 LSB. It is about a 9 dB improvement.

 

I have also tried values of 3.3 kOhm and 12 kOhm, but then the noise tends to increase. So there seems to be a sweet spot here of this resistor value.

 

Some applications rightfully note that you should be aware of sufficient time for the internal SAR capacitors of the ADC to charge, and discharge from previous ADC conversion. I want to limit the previous charge to less than a ½ LSB of the 12 bits, and it is within 1/8192 in value, and you need 9 RC time constants for that. Therefore, you need a RC time constant below 294 ns/9 = 33 ns. According to datasheet the internal SAR capacitance is 5 pF. So, the calculated resistance becomes 6.5 kOhm – or close to the selected value of 6.8 kOhm.

 

I think that you can have some common GND wires inside the chip or some inductive coupling with high frequency spikes, that can change the charged value just before the sampling switches switches off. With a low driving impedance such a spike has larger influence on the remaining voltage on the SAR capacitance. The series resistor causes the SAR capacitance to act as a filter by itself and reduce this effect.

 

The test circuit I use is open with about 10 cm wires, so this is no proof. But if you are interested in lower noise at moderate conversion speeds, I think you should consider trying a series resistor there.

[AScha.3]

Your wrong.

On these kind of ADC you always need low impedance at input, preferably a cer. cap with 10 or 100 nF direct to ground. 

If you want to know why, read about "charge redistribution ADC" , then you should understand.

The maximum impedance depends on sampling time and there is a table with values in the RM.

And have very short wire to the cap or impedance buffer amp, as on high resolution ADC you get many millivolts RF even on 50mm wire to ground.

[Backflip]

I think you are right and I was wrong. I repeated the test with the 100 nF decoupling brown capacitor closer to the PCB as you see here. But I use the normal power GND here, because it is closer.
 

This reduced the measured noise to about 3 LSB peak-peak. The same schematic with about 100 mm long wires to the decoupling capacitor resulted in 33 LSB peak-peak as reported before. Apparently the possible inductive loop here could pick up a significant amount of noise. I know this position of the capacitor is still not perfect, and could be made better when you make a PCB design.
 

I did also try to add the resistor in this situation like this:
 

This resulted in higher noise values and about 10 LSB peak-peak.

So now I am sorry to have made this post, but at least it can illustrate that such external wiring can pick up significant noise.

[waclawek.jan]

The primary concern is that the measured value is not a true representation of input signal. Noise is somewhat secondary, and its reasons are more complex - IMO mostly crosstalk between the input signal and VREF+, possibly through ground impedance; but maybe other crostallks too. The ‘G4 ADC (or analog portion in general) in particular has its share of issues, as witnessed by ‘G4 ADC-related appnotes and the ‘G4-specific ADC appnote.

The concept of “let’s improve big output impedance of the signal source by using a huge capacitor” as a panacea is fundamentally flawed. Let’s assume you have the pot’s wiper at its middle, 50k, and the sampling capacitor is fully discharged at the beginning of sampling, which in practice is not, but we can’t be sure as there’s no guarantee for that and have to account for the worst case. That means that you are charging a 5pF capacitor to 1.5V each 294ns, that gives you an average current (smoothed out by the 100nF capacitor) of 5pF*1.5V/294ns = 25.5uA. That current is drawn through the 50kOhm portion of the pot, adding up to the “normal” divider current of 3V/100kOhm=30uA. Guess what’s the result.

For R>6.5kOhm this compounds with the fact that the sampling capacitor does not succeed to fully charge.

So, you either perform all these calculations for worst case, and change sampling rate accordingly; or spare yourself some disappointment and use an opamp-based buffer.

JW

[Backflip]

I don’t agree with you calculation, because your calculated currents are short term - not long term. I measure only once each second. With a 25 kOhm driving resistance from the potentiometer, you have a time constant for charging the 100 nF of 2.5 ms. So you got 400 time constants of charging in 1 second, and therefore it will get to the intended voltage in one second. As I stated - 9 time constants in time are sufficient to get within ½ LSB of intended value of a 12 bit signal.

Anyway as I already reported, the problem I got was too long wires for the decoupling capacitor.

[MasterT]

Study differential mode of the ADC, it helps a lot to reject noise over wiring. Simple twisted pair attenuates over 50 dB according to this paper.

 

[LCE]

1. “AGND” should be connected to the common GND plane, as low impedance as possible. It would be nice to have the VDDA buffering cap(s) directly at the VDDA & AGND pins, but with the many ADC inputs all over the package, there’s no use connecting the ADC input RCs to AGND. Just make sure that the ADC input RCs are as close to the ADC input pin as possible, without any noisy digital IO adjacent - if possible.
2. The Nucleos… great & inexpensive tools, but the PCB layout was made for many different uses, not much for the ADC inputs. There are some terribly long tracks running all around the board, due to solder bridge and connector options.

So with better placement and layout, signal quality will probably reach the number of bits as advertised, but also depending on the sampling rate.

And as Jan said, in case of doubt a big cap might not be good enough, so a driver op- / dif-amp and using differential inputs might be required.

I use the STM32’s ADC on all types (H7, G4, L0) that I use, but only for DC voltage monitoring. And for that 1k / 10nF (+ a possible not too high resisitvie divider) at single-ended and some oversampling is by far good enough.

[Backflip]

​@LCE 

Yes, I agree.

In general it is very difficult to maintain a concept of separate GNDs and this AGND. The main issue is, that you need a GND plane with no big holes to keep a low impedance at high frequencies. Tracks will be more subjected to inductive coupling and got higher inductance. I think extending an AGND outside a PCB will start to cause more problems than it might solve. So for a solid first design I would first go for one GND as a GND-plane for both AGND and and GND. In this way you will be able to keep a good reference for the driving circuit to the analog input pin.

I got a documentation with the schematics for the Nucleo64 STM32G4 boards, MB1367, but it do not include the actual PCB layout regarding GND-planes and tracks. Have the layout been published for the Nucleo boards?

[Backflip]

I did find the NUCLEO PCB-layout under “Manufacturing files” here:
https://www.st.com/en/evaluation-tools/nucleo-g474re.html#cad-resources

[creativeshelf37]

That's an interesting observation, and your measurements make the discussion much more useful than the usual "always use a low impedance source" recommendation.

One thing worth considering is that the series resistor and the external capacitor are forming more than just a source impedance—they're also isolating the ADC's sample-and-hold capacitor from high-frequency disturbances. If the resistor is too small, the sampling capacitor can directly "see" switching noise from the MCU, supply rails, or PCB parasitics. If it's too large, however, the sample-and-hold capacitor may not settle completely within the acquisition time, introducing conversion error.

That would explain why you found a sweet spot around 6.8 kΩ instead of seeing a monotonic improvement. In other words, there is a trade-off between noise filtering and settling accuracy.

It would also be interesting to repeat the experiment while varying:

• The ADC sample time (longer acquisition windows).
• The external capacitor value (e.g., 1 nF, 10 nF, 100 nF).
• Continuous conversion versus one sample per second.
• A proper PCB layout with a low-noise voltage reference instead of flying wires.

If the optimum resistor shifts with sample time, that would strongly support the settling-time explanation. If it remains around the same value, it could point more toward internal switching noise or coupling inside the MCU.

Thanks for sharing the data—it's a good reminder that the "lowest possible source impedance is always best" rule isn't universally true for SAR ADCs, especially when practical noise sources are involved

[Backflip]

​@creativeshelf37  Thanks for your reply. I think you got the point I was trying to make.

I hope you did see my response with new measurement results in my reply to ​@AScha.3 

It can be hard to determine what the main noise contributors are in each case. In my case it was the external long wiring to the decoupling capacitor that caused most of the noise in the first measurements. But with a better PCB layout for an application this can be done much better. In my later measurements, an important source to noise may be capacitive coupling from digital signals to the input pin area. I don’t know for sure and different approaches for noise reduction will apply.  
 

[waclawek.jan]

> I don’t agree with you calculation, because your calculated currents are short term - not long term. I measure only once each second.

Fair, I’ve missed the “once per second” part, that of course makes all the difference. And the calculation has to be done.

My problem is presenting the capacitor as a solution to the high signal impedance problem, without being explicit that it implies sample rate limitation.

And if you are going to work with the ‘G4 ADC, I still recommend you to read the errata and the ‘G4-ADC-specific appnote I mentioned above.

JW