STM32G4 ADC: Clarification on exact execution order of Offset and Gain Compensation at 10-bit resolution
Hello ST Community,
I am working with the STM32G4 ADC and am experiencing a conflict between my understanding of the internal digital processing pipeline and the behavior I am observing when combining Offset Correction and Gain Compensation at a reduced resolution (10-bit).
According to the reference manual (RM0440), the digital processing back-end handles data in a specific sequence. However, I need absolute clarification on the mathematical interaction between ADC_OFRx and ADC_GCOMP.
My Setup:
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MCU: STM32G4 Series
-
ADC Resolution: 10-Bit (
ADC_RESOLUTION_10B) -
Gain Compensation Factor: 16383 (Maximum 14-bit value, which equals a ~4x multiplier)
-
Offset Sign: Negative (
ADC_OFFSET_SIGN_NEGATIVE)
My Configuration Code:
// Resolution configuration
ADC_Head->Init.Resolution = ADC_RESOLUTION_10B;
ADC_Head->Init.DataAlign = ADC_DATAALIGN_RIGHT;
// ... standard HAL init ...
// Apply maximum gain compensation (~4x)
LL_ADC_SetGainCompensation(ADC_Head->Instance, 16383);My offset setting code:
uint32_t tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(ADC_Head, offset);
LL_ADC_SetOffset(ADC_Head->Instance, ADC_OFFSET_1, ADC_Channel, tmpOffsetShifted);
LL_ADC_SetOffsetSign(ADC_Head->Instance, ADC_OFFSET_1, ADC_OFFSET_SIGN_NEGATIVE);
LL_ADC_SetOffsetSaturation(ADC_Head->Instance, ADC_OFFSET_1, LL_ADC_OFFSET_SATURATION_ENABLE);The Dilemma & Observations:
Because the ADC_OFFSET_SHIFT_RESOLUTION macro left-shifts the offset value by 2 bits for 10-bit mode, the maximum value I can pass to my offset variable is 1023. If I pass 1024, it left-shifts to 4096 (0x1000), overflowing the 12-bit OFFSETy[11:0] register and flipping back to 0.
I am trying to achieve an effective post-gain offset reduction of 1600 in the 10-bit domain.
-
Hypothesis A (Offset applied BEFORE Gain): If offset is applied first in the 12-bit domain, then to get a final reduction of 1600, my raw offset should be divided by the gain factor ($1600 / 4 = 400$). I would program
offset = 400, which safely avoids the 1023 register overflow. -
Hypothesis B (Gain applied BEFORE Offset): If gain happens first, I would need to subtract 1600 directly. But I cannot program
offset = 1600because the 12-bit register flips at 1023 due to the macro shift.
In my bench testing, I am observing behavior that matches Hypothesis B (the offset behaves as if it is applied after the gain stage, or it is simply not being amplified by the gain factor). An offset of 100 counts reduces my final gained output by exactly 100 counts.
Could an ST engineer clarify the exact hardware equations running inside the digital processing backend? Does the hardware scale the offset register bounds when Gain Compensation is active, or does the subtraction strictly happen on the raw 12-bit padded conversion before the multiplier?
Thank you!
