STM32 MCUs

From my understanding all STM32N6 chips need a external flash chip and there's a static stage 0 boot loader.  So if this is true is there any limitation's on the brands of flash or speed/address bit size limitations? With the previous stage 0 bootloader for a different non ST product had a lot of limitation on the flash that could be used.* 16 bit flash address only* Only support a few brands of flash chips.  

That pretty much says it all.   Any attempt to tear down the connection (disable spi, disable dma, etc) before (long before) stop1 causes flash write after (many instructions after) the wfi to fail with PGSERR error.   Not tearing down the connection, flash write works, but standby doesn’t without additional work.   To be concrete dma3ChannelFreeI(spip->dmatx); if (spip->state == SPI_READY) { /* Just in case this has been called uncleanly.*/ (void) spi_lld_stop_abort(spip); spip->spi->CFG1 &= ~(SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN); spip->spi->CR1 &= ~SPI_CR1_SPE; /* Releasing DMA channels.*/ dma3ChannelFreeI(spip->dmarx); dma3ChannelFreeI(spip->dmatx); Those two lines -- spip->spi→… are what break flash write.  Clearly there is an undocumented interaction between peripherals and the clock and data transfer system, but the documentation for the part is shockingly incomplete on important details such as this.Leaving those lines out

Hello everyone,I'm trying to configure the SAI and GPDMA peripherals on an STM32 to acquire audio from an I2S microphone. My goal is to capture a 32-bit, 2-channel audio stream at a 16 kHz sample rate, with the STM32 acting as the clock master. I've followed the steps below, but I'm running into two main issues:While the HAL_SAI_RxCpltCallback and HAL_SAI_RxHalfCpltCallback functions are being called, the acquisition buffer remains unchanged (full of zeros).I'm seeing a 16 kHz signal on all three I2S lines (SCK, FS, and SD), which is incorrect. The clock (SCK) should be much higher.Here's a summary of the steps I've taken:PLL4 Configuration: I've configured PLL4 to generate a 1.024 MHz clock (16 kHz * 64 = 1.024 MHz). This clock feeds into the IC7 peripheral.GPDMA1 Configuration: I've enabled the clock and interrupts for GPDMA1 Channel 0 and added a linked-list initialization.SAI1 Block B1 Configuration: I've set up the SAI handle for I2S standard, 32-bit data, 16 kHz audio frequency,

Hi.I’m using CubeIDE, CubeMX and HAL to create an application for an STM32L451.I’ve setup USART1 to receive via DMA in circular mode and detect line idle, starting receptions with HAL_UARTEx_ReceiveToIdle_DMA(), and processing receptions in callback HAL_UARTEx_RxEventCallback().All seems to work fine except that the TC (transfer complete, or full buffer) interrupt never happens.HT (half transfer, or half of the buffer reached) and line idle do interrupt.I’m providing HAL_UARTEx_ReceiveToIdle_DMA() a buffer of size 128 bytes. I’m logging the value of the size argument to HAL_UARTEx_RxEventCallback(). When I manually send a message of 20 bytes repeatedly, but slowly enough to ensure line idle triggers, the callback is called with the following size values: 20, 40, 60, 64, 80, 100, 120, 120, 12, 32, 52, 64, 72, 92, 112, 112, 4, 24, (etc).You can see that line idle works, and also that HT is issued in the middle of a reception (size == 64), but TC isn’t, there’s no size equal to 128.What’s

I am trying to generate an interrupt when the HSP finishes a processing list so that I don’t need to poll it. However, I can’t seem to figure out how to do this.There are some things in the STM32U3 reference manual that make me confused:In section 19.4.12 HSP interrupt controller (HITC), there are four interrupt lines:• An interrupt line handling errors (hsp_err_it)• An interrupt line handling various hardware events (hsp_evt_it)• An interrupt line handling events generated by the SPE processing (hsp_fwevt_it)• A global interrupt is asserted when one of the previous interrupts is asserted (hsp_it)However, in Section 19.3 HSP Implementation, Table 143 shows that neither hsp_err_it, hsp_evt_it, nor hsp_fwevt_it are implemented in the U3 series. If this is the case, does that mean that hsp_it is just never asserted? Is it possible to notify the application when a processing list has finished without polling for a flag?Section 5.13.5 of UM3360: HSP processing functions says that the SET_FL

Hi ,I am using STM32H573VIT3Q MCU, I need USB so i am using internal PHY. I configured all in cubeMx all other things are working well only problem is with USB. I have tried both Host and Device modes but nothing works. Then i created a test project only for USB in device mode, I have connected the logic analyser on USB pins to see the data , but no single pulse is there if i plug/ unplug the usb cable to PC. I have attached this full project as well for your reference. I have tried GPIO toggle to confirm all connection are ok and well soldered. Here is my circuit diagram of MCU.I have also attached my IOC files. Please help me to solve this error. Thanks

Hello , While configuring the I2S1 why i cant  find its reference on the GPDMA1? Is it not available for DMA transfers?All other peripherals are available ( like uart,SPI,I2C but not I2S).Here is the snapshot.Regards,D

Hello ST Community,I am facing a critical issue while configuring OEMiRoT on an STM32H523 device. I used the official provisioning project from the NUCLEO-H533RE example in STM32Cube_FW_H5_V1.7.0 (since there is no dedicated H523 example). I need help recovering the device.Background: I‘ve modified the <DoEncryption> value to 0 according to ‘How to create ROT examples for STM32H5’. I ran the provisioning project (from the NUCLEO-H533RE example) to configure OEMiRoT on the target STM32H523 device. During provisioning, the configuration failed and the product state became Provisioned. After that, the device could no longer be connected via ST-LINK SWD. DA also failed. Then I regenerated a new Key file to confirm if there was any problem during the configuration process. I still have the private key file key_1_root.pem . But the public key file key_1_root_pub.pem and certificate file cert_root.cert have been overwritten. So I tried the method provided by the AI assistant to

Dear STM32 Advisor,   I'll design a system based on Nucleo 64 H533RE. The system will act as USB CDC and USB HID Keyboard at the same time. The idea is when the CDC receive a character, here for example "F" then the Nucleo H533RE will output a high going pulse. And, if the Nucleo H533RE receive falling pulse external interrupt, the the Nucleo H533RE will press the F8 key. As a beginner on STM32, is it possible?   Thanks and regards,   Fuad Purnomo.

I have a question regarding your company’s NUCLEO-H753ZI model.I evaluated two boards of this model (let’s call them a and b), and observed the following phenomenon exclusively on ADC channel 2 of board a. [Phenomenon]When we applied various input voltages and measured the output, we found that the output dropped by approximately 800 LSB (equivalent to about 0.04 V) within the input voltage ranges of 0.825–1.65 V and 2.475–3.3 V (1/4–2/4 and 3/4–4/4 of full scale).*The input voltage conditions (accuracy, ripple) were identical across all boards and channels. [Board Information]ADC Channel 2 Assignment: PA3Resolution: 16-bit modeSampling Time: 16.5 cyclesSampling Frequency: 250 kHz (timer-triggered) Since this phenomenon is not observed on other boards or channels, we suspect that some kind of malfunction is occurring. Based on the symptoms, we also suspect a failure within the successive approximation ADC. If you know the cause of this phenomenon, please let us know.Also, if there are

Moving the motor in small steps how to avoid phantom steps, I notice for example the the stepper moves 50 times 10 steps, moves 15 to 25 more steps, could you describe how to stop when a motion is completed.ATT  

Hello ST Community,We are working with the STM32N657X0H3Q controller and interfacing an S80KS5123GABHB020 HyperRAM using the XSPI1 (Octal SPI) interface. The external HyperRAM is intended to be used as the LTDC frame buffer.We have configured the HyperRAM in memory-mapped mode, and according to our configuration, it should be accessible at the address 0x90000000.However, we are unable to access this memory region. Any read or write operation to 0x90000000 fails. For initial testing, we have configured the XSPI clock to 2 MHz.Our setup is based on the STM32N657-DK board example, and we have followed the same memory-mapped configuration.Could you please let us know if any additional configuration is required to access the HyperRAM at 0x90000000? Specifically, we would like to know:Are there any additional XSPI configurations required for memory-mapped mode? Does the MPU or cache need to be configured for this external memory region? Are there any system, clock, or pin configurations that

In TouchGFX/target/generated/OSWrappers.cpp at row 38 & 39 the lines : static TX_SEMAPHORE frame_buffer_sem = { 0 };static TX_QUEUE vsync_q = { 0 };will produce a GCC compiler error when the compiler settings are set at -Werror. error: missing initializer for member 'TX_SEMAPHORE_STRUCT::tx_semaphore_name' [-Werror=missing-field-initializers]Compiled with these relevant flagsarm-none-eabi-g++ "../TouchGFX/target/generated/OSWrappers.cpp" -mcpu=cortex-m7 -std=gnu++17 -g3 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -Wextra -Werror  

We are designing an independent current monitoring circuit for a motor driven by the powerSTEP01. We are using a 0.1 ohm low-side sense resistor (RSENSE).When probing the voltage across this sense resistor with an oscilloscope, we are observing a distinct PWM waveform where the negative voltage pulses have almost the exact same amplitude as the positive voltage pulses (flipping symmetrically below ground, e.g., +0.5V and -0.5V. )Screenshot: RSENSE voltage generated across 0.1ohm when motor is rotating in current mode  Before I modify my external analog front-end (currently using an RC filter, a clamp diode and an op-amp) to handle these negative swings, I want to double-check my findings.Is this symmetrical negative voltage pulse an expected physical phenomenon of the powerSTEP01 H-bridge operating in Fast Decay / synchronous rectification mode? Or am I likely dealing with an oscilloscope probing/grounding issue, such as ground bounce or parasitic inductance artifacts?Any insights into

I am working with an STM32H743VIT6 and I am trying to migrate an existing bare-metal LVGL + SDMMC + FatFs project to FreeRTOS + LVGL + SDMMC + FatFsIn my previous bare-metal project, the SD card worked correctly.However, after creating a new project using STM32CubeMX with FreeRTOS + SDMMC + FatFs, the FatFs mount operation fails from the beginning.The problem occurs when calling:f_mount(&SDFatFS, SDPath, 1);void LVGL_Task(void *argument) { (void)argument; printf("LVGL Task START\r\n"); FRESULT fres; printf("before f_mount\r\n"); fres = f_mount(&SDFatFS, (TCHAR const *)SDPath, 1); printf("after f_mount, result = %d\r\n", fres); if (fres == FR_OK) { printf("SD success\r\n"); } else { printf("SD fail\r\n"); } printf("before ui_init\r\n"); ui_init(); printf("after ui_init\r\n"); while (1) { uint32_t delay = lv_timer_handler(); if (delay > 1000) delay = 10; osDelay(delay); }} I have placed the buf address in AXI SRAM and confirmed that the addres

HiI recently received a NUCLEO-WB55RG (the big board, not the USB dongle) and tried installing the demo from the STM32CubeWB repository.I saw that I need to flash the FUS + Stack first which I did. STM32CubeProg reports FUS State: FUS_IDLEFUS Status: FUS_NO_ERRORFUS Version: V2.2.0.0STACK Version: V1.24.0.3STACK Address: 0x80D0000FUS Operator: v3.1.0The files I flashed were:STM32CubeWB-master\Projects\STM32WB_Copro_Wireless_Binaries\STM32WB5x\stm32wb5x_BLE_Stack_full_fw.binSTM32CubeWB-master\Projects\STM32WB_Copro_Wireless_Binaries\STM32WB5x\stm32wb5x_FUS_fw.binAs application I chose the p2pServer applicationSTM32CubeWB-master\Projects\P-NUCLEO-WB55.Nucleo\Applications\BLE\BLE_p2pServer\Binary\BLE_p2pServer_reference.hexWhen I disconnect the SWD Interface and press the reset button I get the following output (nothing else):Wireless Firmware version 1.24.0 Wireless Firmware build 3 FUS version 2.2.0 >>== SHCI_SUB_EVT_CODE_READY >>== SHCI_SUB_EVT_CODE_READY - FUS_FW

Currently we are developing an AI Industrial camera using STM32N6570, we are exploring the compatible SPI Flash for the implementation. Could you share your recomendation of 1Gb Octal SPI Flash.

Hello,I have encountered a critical issue regarding the USB OTG peripheral FIFO allocation during the static initialization phase (before calling HAL_PCD_Start() ).The Issue:If I resize the Rx/Tx FIFOs twice with the sequence of "Large Size first, then Small Size", the Endpoint 0 (EP0 IN) completely fails to transmit any data (it freezes/stalls) after the hardware starts.Scenario A (Works perfectly): Set Rx FIFO to 0x100 (Words) ➡️ Set Tx FIFO 0 to 0x16. (Single configuration works). Scenario B (Fails completely): First call: Set Rx FIFO to 0x100, Tx FIFO 0 to 0x16. Second call (immediately after): Set Rx FIFO to 0x25, Tx FIFO 0 to 0x16.Result: EP0 IN never transmits any packet afterward.My ultimate goal is to dynamically reconfigure and shrink the FIFO layout at runtime when receiving the SET_CONFIGURATION request from the host, allowing the device to adapt to different configurations

Hello,I am using an NUCLEO-N657X0-Q (STM32N657) and developing an application using the FSBL + XIP application structure. Development EnvironmentSTM32CubeIDE: 2.2.0 STM32CubeMX: 6.18.1 STM32CubeProgrammer: 2.22.0 The application is stored in external Flash and executed in XIP mode. I can successfully program the external Flash and enter/run the Appli project through the debugger.The application works normally as long as I do not enable the timer update interrupt.However, when I enable a TIM update interrupt in the Appli project, the application stops working when the interrupt occurs.My project structure is:FSBL └─ Initializes the external Flash and starts the XIP applicationAppli └─ Executed from external Flash └─ TIM update interrupt enabled hereThe timer itself is initialized in the Appli project.The interrupt handler is also located in the Appli project's stm32n6xx_it.c:extern TIM_HandleTypeDef htim1;void TIM1_UP_IRQHandler(void){ HAL_TIM_IRQHandler(&htim1);}and the call

Hi,We have configured PB11 and PC4 for UART. when UART send data, what is pin current sourcing capacity?/Anurag  

I want to make the CustomScrollTimeTextCenter fully visible, without being cut off by anything else, and without leaving any extra gaps.But it's this kind of effect, I've tried adjusting all sorts of parameters, and I still can't get the effect I want.I want this kind of effect：Here's an introduction to the problem：I have two custom components of different heightsCustomScrollTimeTextCenter 70CustomScrollTimeText 44 

I am using open bootloader in stm32g0b1kct6 and when i am flashing it and then flashing application code over CAN it is only working while debugging and as soon as i flash application code it stopped working. Both are working fine in debugging but not when hex flashed and also when bootloader is working in debugging and i flash application code it stopped working immediately.

Environment - Device: STM32H562ZI- Reference manual: RM0481 Rev 5- HAL: STM32Cube H5 HAL Driver V1.5.0- Peripherals: GPDMA used for SPI slave Tx/Rx. SPI in slave mode, normal (non-circular) transfers, no linked-list. Summary On our SPI slave DMA path, the DMA channel becomes permanently stuck after an SPI error, and SPI communication never recovers until the device is power-cycled. The cause is that `GPDMA_CxCR.SUSP` gets written to a channel that has **already completed its transfer and stopped** (EN=0, IDLEF=1). In that state `GPDMA_CxSR.SUSPF` is never set, so `GPDMA_CxCR.RESET` is never written and **SUSP stays set**. Setting `EN=1` afterwards suspends the channel immediately after start, and the driver can no longer escape that state. Observed register sequence (Tx channel, real measurements) ```1) Block transfer completes. Hardware clears EN.CxCR = 0x00805D00 (EN=0, SUSP=0, SUSPIE=0)CxSR = 0x00000001 (IDLEF=1) 2) An SPI error occurs right after this point.SPI ErrorCode = 0x84 (UD

Hi,I am trying to initialize FDCAN for my project. After the initialization I am clearing INIT bit in CCCR Register. The output what I can see is only CCE bit gets cleared but INIT bit is stuck at 1.Below is my code snippet.void Can_driver_init (void){ uint32_t StartAddress_l_u32 = CAN_RAM_OFFSET_CFG; uint32_t RAMcounter_l_u32  = 0; uint32_t ElementSize_l_u32 = (CAN_DATA_BYTES_CFG/4); // Enable the peripheral clock for FDCAN RCC->APB1HENR |= RCC_APB1HENR_FDCANEN; // Exit from Sleep mode */ CAN->CCCR  &= ~FDCAN_CCCR_CSR; // Wait till the CSR bit is set in CCCR */ while (CAN->CCCR == FDCAN_CCCR_CSR); // Wait timeout to be added // Request initialization */ CAN->CCCR  |= FDCAN_CCCR_INIT; // Wait until the INIT bit in CCCR register is set */ while ((CAN->CCCR & FDCAN_CCCR_INIT) != FDCAN_CCCR_INIT); // Wait timeout to be added // Enable configuration change */ CAN->CCCR  |= FDCAN_CCCR_CCE; // Enable automatic retransmission

Hi, I have 2 questions here for help.1.)We encountered 2 x AAA batteries drained out very fast problem feedback by our customer. In order to resolve this problem I enabled STOP2 mode and added in the following 2 lines of codes in function “APP_Zigbee_NwkForm()” which following exactly the sample project did (Zigbee_OnOff_Client_SED). As the result I can see the battery consumption dropped significantly from mA to uA. However, during the functional test, noticed the device always encountered hardly wake up from the STOP2 mode after multiples times of button pressing action. I cannot find much information about these 2 lines of codes therefore request ST’s expertise to help up. Our production line has stop and waiting for my firmware update in order to resume.  /* Add End device configuration */config.capability &= ~(MCP_ASSOC_CAP_RXONIDLE | MCP_ASSOC_CAP_DEV_TYPE | MCP_ASSOC_CAP_ALT_COORD);config.endDeviceTimeout=ZED_SLEEP_TIME_30S;   2.)I noticed that, after added in these 2 lines