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For the SMPS mode of the STM32H563MIY3Q, the datasheet recommends an inductor with an RMS current (Irms) rating of 1.4 A. However, the actual core current is only 50 mA. Is it acceptable to select an inductor with a lower Irms rating, such as 500 mA?

Hi,what would be recommended way to override internal LDO which is used for VDD11/VCAP preparation? Because of thermal management, we prepared external LDO to lower internal MCU temperature. In H5 family, there was an BYPASS bit in PWR management. Maybe shall I change Vos to lower level to let higher level LDO win? Or would you have other way :) Thanks!JM

Hello,I am using the ST25R200 evaluation board with the STSW-ST25R020 firmware package.I am planning to develop a custom Python GUI that displays a specific text string whenever an NFC tag is detected by the board. To achieve this, I want to modify the C firmware so it actively streams out a text string via UART/VCP as soon as a tag enters the field.Could you please guide me on the following?Which specific source file and function in the STSW-ST25R020 package handle the successful tag detection/inventory loop where the tag's UID is retrieved? Where is the best place to insert a custom printf or logging function to stream this text data out via UART immediately upon detection? Thank you very much for your help!

Hi,the cubemx HRTIM configuration will not let me set the set sources for Output 2, even though deadtime insertion is turned off.I had previously enabled it, and now disabled it. Since then I am unable to add a set source for Output 2.See the attached screenshots and .ioc file.I am using version 6.17.0

I'm investigating a suspected flash corruption/ECC issue on an STM32H743.A read from flash address 0x081F0000 consistently causes a fault. The problem is that I'm not fully confident that the fault status registers can be trusted after the event, so I'm looking for a diagnostic approach that does not rely entirely on the captured fault information.Known facts:Accessing 0x081F0000 triggers a fault. ECC_FA2R does not show a failing address. STM32H7 flash ECC is evaluated only when flash is read. ECC granularity is 32 bytes (256 bits).My main question is:If I suspect flash corruption or an ECC problem, but do not fully trust the contents of CFSR, HFSR, BFAR, SR2, or ECC_FA2R after the fault, what is the recommended way to diagnose the problem?Would you:Perform a controlled BusFault-protected flash scan in 32-byte steps? Use HAL_FLASHEx_ComputeCRC() over the suspect region? Dump the entire flash bank via SWD/JTAG and verify externally? Use some other method?Has anyone seen a corrupted flas

Title shortened from:"With the STM32U545RE, unable to erase the correct Flash Bank, using HAL_FLASHEx_Erase(), when attempting to switch from Bank2 to Bank1".Please keep the title short. Testing is done with the Nulceo-U545RE-Q board having 512KB Flash organized in two Banks. Each Bank has 32 pages of 8KB each. Flash Bank1: 0-31 pages. Flash Bank2: 32-63 pages. I could switch-over from Firmware-Version1 executing in Bank1 to Firmware-Version2 executing in Bank2. I verified that Firmware-Version2 was executing correctly even after hardware reset and power cycle.Attempting to switch-over  from Firmware-Version2 executing in Bank2 to Firmware-Version3 executing in Bank1 fails as I end up erasing the Bank with the currently executing software(Firmware-Version2). I checked the setting of the SWAP_BANK bit and then erased the Bank, using the code below:  /* Get the boot configuration status */ HAL_FLASHEx_OBGetConfig(&OBInit); /* Check Swap Flash banks statu

Hi, Could you please confirm whether an external NFC antenna can be connected to the X-NUCLEO-NFC08A1 board? I see P200 and P202 in the schematic, but it is not clear to me whether these are intended for external antenna connection or only for optional/test points. If an external antenna can be used, could you explain how the on-board etched PCB antenna should be disconnected from the ST25R3916B antenna path, where the external antenna should be connected instead, and what antenna inductance or electrical parameters should be targeted before tuning the matching network?Thanks!Best regards, Jose 

We are currently working on a project using the STM32H750IBT6 microcontroller interfaced with a single-bank Quad SPI NOR Flash (MT25QL512ABB) on our custom board. The QSPI interface is operational.However, we are facing an issue with the external loader. While the same external loader setup works correctly with the STM32H750 development board using the same two MT25QL512ABB Flash memories, it fails to function on our custom board.Development board QSPI schematic: Our custom board QSPI schematic: For reference, we are used the external loader implementation for development board from the following link: https://controllerstech.com/w25q-flash-series-part-8-quadspi-external-loader/ We request your support in:Verifying if our schematic connections for the QSPI interface may be contributing to the issue.Identifying any possible hardware or configuration-related causes for the external loader failure.

Hi We are developing a board with the STM32U073CCT6 CPU. Would it be possible to use a crystal with the following characteristics for the LSE?32.768KHz Cl=6pF/ESR=50kRIn this case, what would be the recommended capacitor values?BRGilberto 

Hello, I am trying to connect to the STM32F072C8T6 microcontroller via USB in the STM32CubeProgrammer, however I am getting:"Device is under read out protection ! If you want to disable RDP please reconnect with Read Unprotect enabled"So, when I check the Read Unprotect (MCU) checkbox, I get:"Please Power off Power on your device."After turning the power off/on, I see the same messages. I cannot connect to the MCU via USB in the STM32CubeProgrammer.I have tried different versions of STM32CubeProgrammer:v2.16.0v2.15.0v.2.13.0v.2.10.0v.2.8.0Moreover I tried on second computer with Windows 11 and I have the same issue.I'm trying to connect my custom board, but I also checked another hardware board (BluePill ) with the same STM32F072C8T6 MCU and it doesn't work either.Interestingly, using the DFU-util v0.8 program I can connect to the MCU and successfully read/write memory:  

I am using ADXL203  analog inclinometer. I would to compensate the offset variation with temperature.As the ADXL203 itself does not have an internal temperature sensor, could you give me any advice on how to measure the temperature?Thank anybody for the attention.GF 

hifor stm32G4 series, if MCU option byte IWDG_SW equal TRUE, and the software start the IWDG by calling HAL_IWDG_Init(),when a system reset happen( for example, call HAL_NVIC_SystemReset() or IWDG reset), will IWDG stop counting before  next time initialization?  

Hello, I have a STM32F401RCT connected to a ST25R100.In the ioc file I enabled the X-CUBE-NFC9 library with all the necesary dependencies.All the IOs also have pins assigned to them.Plus Pull ups enabled on the IRQ (open drain) and NFC_Reset.Currently I have found out that it crashes somewhere after MX_X_CUBE_NFC9_Init();ret code: 0NFC BSP COM = 100Welcome to X-NUCLEO-NFC09A1 entered error handlerThis is what I get in my console. I added some printfs in the code already.When I run it in debug mode to check were it calls the error handler it for some reason does not hit the error handler but it gets stuck in stm32F4xx_il_usb.c; when I click pauze, this seems rather odd.HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num){ __IO uint32_t count = 0U; /* Wait for AHB master IDLE state. */ do { count++; if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); /* Flush TX Fifo

Hi, I met a strange issue of ADC overrun during flash erase.The ADC is configured with circular DMA+TIM3 triggered at 1khz:static void ADC_Config(void) { /* Enable clock */ RCC->AHBENR |= RCC_AHBENR_DMA1EN; RCC->APBENR2 |= RCC_APBENR2_ADCEN; RCC->APBENR1 |= RCC_APBENR1_TIM3EN; /* ADC Init */ ADC1->CR |= ADC_CR_ADVREGEN; uint32_t tick = SysTick->VAL; /* Startup delay */ while ((tick - SysTick->VAL) < 960); /* Calibration */ ADC1->CR |= ADC_CR_ADCAL; while (ADC1->CR & ADC_CR_ADCAL); /* TIM3 trigger, DMA enable */ ADC1->CFGR1 = ADC_CFGR1_EXTEN_0 | 3 << ADC_CFGR1_EXTSEL_Pos | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN; /* Use 14MHz ADC clock */ ADC1->CFGR2 = ADC_CFGR2_CKMODE_0; /* Enable overrun interrupt */ ADC1->IER = ADC_IER_OVRIE; /* Long sampling time */ ADC1->SMPR = ADC_SMPR_SMP1_0 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_2; /* Vref and Tint enable */ ADC1->CHSELR = ADC_CHSELR_CHSEL

HI How are you!I am using the SAI interface on the STM32MP257F-DK to connect directly to an external ADC and acquire data in frame mode. I have assigned SAI3 to the M33 domain and run the firmware under FreeRTOS. Despite following all resource isolation configurations specified in the reference manual and conducting a full week of detailed debugging and security settings, launching the M33 firmware remotely from the A35 Linux domain always results in an IAC error. Is it not possible to assign the SAI peripheral to the M33 core?  thanks !

HiI'm looking for STM32 Nucleo boards or similar microcontroller boards that have embedded SIM (eSIM) capabilities. However, I haven't been able to find any boards that directly support eSIM integration. Are there any Nucleo boards that are compatible with eSIM modules like ST4SIM, and how can I identify or find them?Thanks and Regards@avbST 

Hi, according STM32H743 datasheet VDDLDO pin in BGA packages can be supplied independently from VDD pins. The problem is that on STM32H743VIH BGA package VDDLDO and VDD physically shorted in the package. Is the datasheet misleading or I’m missing  something?  

eg, see here: https://www.st.com/resource/en/user_manual/um1690-discovery-kit-for-stm32f0-series-microcontrollers-with-stm32f072rb-stmicroelectronics.pdf#page=13 The #page=13 should be included in the URL, so that the linked PDF opens at page 13

Dear ST Support Team,Thank you for your continued support. We are working with the STM32MP257F-EV1 evaluation board and have two issues we need help resolving.Hardware: STM32MP257F-EV1 Evaluation Board (MB1936D)Software Package: OpenSTLinux v26.02.18 (stm32mp2-openstlinux-6.6-yocto-scarthgap-mpu-v26.02.18)Host OS: Ubuntu 26.04STM32CubeIDE: v2.1.1STM32CubeProgrammer: v2.22.0Flash Layout Used: FlashLayout_sdcard_stm32mp257f-ev1-ca35tdcid-ostl-m33-examples-optee.tsv---ISSUE 1: ETHERNET PORT (end0 / ETH1) NOT WORKING---The Ethernet interface end0 shows NO-CARRIER even when a cable is physically connected.Observations:- ip link show end0 → state DOWN, NO-CARRIER- cat /sys/class/net/end0/carrier → 0- ethtool end0 | grep 'Link detected' → Link detected: no- udhcpc -i end0 → broadcasts DHCP but gets no response- The Ethernet driver loads correctly: stm32-dwmac 482d0000.eth2 end0- We have tried ETH1 and ETH2 ports on the board- We have tried different cables and different router ports- The boar

I am using an STM32G030C8T6.I have 10 boards built from the same PCB design and BOM. All boards use the same firmware.8 boards work correctly, but 2 boards show abnormal ADC readings.ADC channels used: PA1 = ADC_IN1 PA5 = ADC_IN5 PA6 = ADC_IN6 PB0 = ADC_IN8 PB1 = ADC_IN9 PB2 = ADC_IN10 VREFINT ADC configuration: 12-bit resolution Continuous conversion enabled Scan conversion enabled DMA circular mode Sampling time = 160.5 cycles VREFINT included in the scan sequence Problem:On the failing boards, when the battery is connected, some ADC channels become 4095.Example:LOAD_I_ADC = 4095PV_A_ADC = 4095BAT_A_ADC = 4095VREFINT_ADC = 4095Other channels still show valid values.Measured VDDA: Battery disconnected: 3.32V Battery connected: 3.33V To isolate the issue, I created a separate test project using only the following: ADC_IN9 (PB1) VREFINT Results with battery disconnected:adcBuf[0] = 1415adcBuf[1] = 1518These values appear normal.I then created another test proje

I’m setting up a new project in STM32CubeMX for an STM32L073RZ using the internal LCD controller in 1/3 bias mode.According to the STM32L0 reference manual (RM0367), the LCD voltage rails should be configured as:PB12 - VLCDrail1PB2 - VLCDrail2 However, in STM32CubeMX, the GPIO configuration only allows:PB12 - VLCDrail2PB2 - VLCDrail2There does not appear to be any option to configure either pin as VLCDrail1.Am I misunderstanding the LCD rail configuration for 1/3 bias mode on STM32L073RZ, or is this a limitation/bug in STM32CubeMX?Thank you!

The STM32G474RE support 3 FDCAN and that fit my design well.  When I checked the nucleo board, the firmware does not have any CAN example.  I searched the ST website, the user, programmer and reference manual do not have any information on the registers and their memory map information.  Although I found “STM32 FDCAN running at 8 Mb/s on Nucleo boards” helpful, it does not give me enough information of the FDCAN 2 & 3’s interrupt vector location, calls, setup and etc.  I need a example template to set up my FDCAN.  Where can I find that?

Hello Friends,I am looking for MCU. Kindly suggest. Below are the minimum requirementsNeed two SPI.  Need to read data of two sensors via SPI simultaneosly & continously. Need one UART  Need smallest possible foot print.  WLCSP12/TSSOP20/UFQFPN20 Do not want to use external cyrstal for clock. Want to use internal clock Robust for shock, vibration.  Pricing is no issue.Kindly suggest..   

Hello ST Team, We are evaluating the STM32H747BIT6 in the LQFP208 package for our application. To verify the feasibility of our design, we created a CubeMX project and configured the required peripherals, including LTDC RGB888 (24-bit), FMC SDRAM (32-bit), USB FS, I2C1/I2C2/I2C3, USART1/USART3, SPI1 and TIM PWM outputs. While configuring the project, CubeMX allowed us to assign all the required signals, and all pins are shown in green. We also checked the LTDC and FMC SDRAM signals and found that they are assigned to unique pins with no visible pin conflicts in the pinout view. Could you also review the attached .ioc file and confirm whether there are any pin conflicts that we may have overlooked? However, CubeMX displays the following warning on the FMC peripheral"Partly disabled conflict with:FMC (SDRAM1): Clock and chip enable SDCKE0 + SDNE0 and/orLTDC: Display Type RGB888 (24 bits)". Could you please help us understand what this warning indicates and why CubeMX is reporting it? We

Split from this post.I’ve just tried testing the out FIFO depth.The STM32F427 is operating at 179.8MHz.The DMA2D is configured for memory-to-memory transfers (so only the out FIFO is used - this is how I intend to configure the peripheral to drive the DAC).The DMA2D dead time is configured for the maximum value (255), which allows one AHB transfer to the DMA2D every 1.4 microseconds.The timer generating the NWAIT signal is held low for several hundred microseconds after the DMA2D is enabled and then generates NWAIT pulses that allow the FMC to write a value every 8 HCLK cycles (every 44.45ns).This is the resulting output on the FMC NWE signal, with the controlling NWAIT signal (from the timer) also shown: This suggests the FIFO depth is 48 (16-bit) words.But what happens next raises another question.  This screenshot shows the first burst of 48 writes to the FMC, followed by the next 3 bursts:The subsequent bursts are only 16 writes long, and the time between them (the first interval i