STM32F427 DMA2D FIFO depth and FMC behavior
Split from this post.
I’ve just tried testing the out FIFO depth.
The STM32F427 is operating at 179.8MHz.
The DMA2D is configured for memory-to-memory transfers (so only the out FIFO is used - this is how I intend to configure the peripheral to drive the DAC).
The DMA2D dead time is configured for the maximum value (255), which allows one AHB transfer to the DMA2D every 1.4 microseconds.
The timer generating the NWAIT signal is held low for several hundred microseconds after the DMA2D is enabled and then generates NWAIT pulses that allow the FMC to write a value every 8 HCLK cycles (every 44.45ns).
This is the resulting output on the FMC NWE signal, with the controlling NWAIT signal (from the timer) also shown:
This suggests the FIFO depth is 48 (16-bit) words.
But what happens next raises another question. This screenshot shows the first burst of 48 writes to the FMC, followed by the next 3 bursts:
The subsequent bursts are only 16 writes long, and the time between them (the first interval is about 1.4 microseconds, subsequent intervals are about 2.8 microseconds) shouldn’t be long enough for enough data to be available in the FIFO to write 16 data values to the FMC (the dead time limitation only permits one AHB access each 1.4 microseconds).
Does that indicate that an AHB access by the DMA2D isn’t a single data value, but is a burst of (16?) data values?
