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Hi,I am using an STM32G0B1VET6. All power rails in my design, including VDDIO2/VDDUSB, are supplied from 3.0 V (2.95 min).I would like to use the USB interface and the built-in USB DFU bootloader for firmware updates.AN2606 states that VDDUSB must be connected to 3.3 V. However, AN4879 appears to specify a USB supply operating range down to 2.7 V, with 3.0 V as the minimum recommended operating voltage in some cases. Based on that, I would expect USB to operate correctly with VDDUSB supplied from 3.0 V.Could you please confirm whether USB DFU is supported on the STM32G0B1 when VDDUSB/VDDIO2 is powered from 3.0 V rather than 3.3 V?The board will be powered from its own 3.0 V supply. For the USB programming connection, I am planning to bring out only three wires:USB D+ USB D− GNDThe USB 5 V VBUS line will not be used to power the board.Are these three connections sufficient for entering the system bootloader and performing a firmware update through USB DFU, or is the USB VBUS line or a s

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I posted on 3rd June and have received emails today saying i have replies. However the topic has now vanished! It is no longer on my topic list or reply list. When i click the link it goes to the main page!!Whats going on!? Hello RAdam.1, Your topic recently received a reply.Topic:  STM32WB05 reboots when starting to advertiseDate: 2026-06-03 10:49 AMDid it solve your problem?Click here to view the reply and mark one as an Accepted Solution.This helps others find helpful answers in the community too!Thanks for being a STMicroelectronics Community member.Your STMicroelectronics Community TeamSTMicroelectronics Community sent this message to richardadamsla@gmail.com.Don't want to receive emails from us? Just click here.

Neither in the front page listing, nor in the individual forums. New threads used to be highlighted in bold on the old forum.

Hello,I'm working with the STM32MP135F-DK kit and I'm trying to understand the correct way to configure interrupt lines (IRQs) for external devices,  specifically for the STPMIC1 in OP-TEE.I have been reading the official documentation and I'm a bit confused about whether it is mandatory to use the dedicated PWR Wake-up pins (WKUP1–WKUP6) for interrupt lines, or if any GPIO can be used.--- What I observed in the reference DTS files: Looking at the OP-TEE device tree (core/arch/arm/dts/stm32mp135f-dk.dts, tag 4.0.0-stm32mp), I can see that all IRQ consumers use EXTI lines above 55: - STPMIC1 interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING> (WKUP1 / PF8) --- My questionsIs it mandatory to use one of the 6 dedicated WKUP pins (EXTI 55–60) for any device IRQ managed by OP-TEE? 

Using a custom board with the stm32l412 chip, after entering stop 2 mode, it measures 380uA instead of about 0.72uA without RTC as stated in datasheet.I know using custom board would get the current consumption to get a bit higher but this is almost ridiculous difference, so I expect that something is off, but not sure where to check.Thanks in advance.

I'm using the mp215 with ddr3l (x16) and an ISSI dram ic that is 8Gb (1 gigabyte) which means it's a dual rank configuration compared to a more typical half gigabyte. As far as im aware all 1GB ddr3 dram ic's are dual rank.In AN5723 6.1 Note it says "8 Gbit DDR3 defined by JEDEC is uncommon. Practically, DDR3L density is limited to 4 Gbits (max = 1 Gbyte in total). Single rank only is required. ".an5723 link As far as I understand it it says it's not possible. However this is an older AN and i think it's for the mp25 series only (im using the mp21).However in the ST Wiki "How to setup the DDR configuration" section 5 the exact opposite is implied. This whole section repeatedly describes a "concrete example" of swapping the swapping the mp215-dk's lpddr4 out with a 1GB ddr3 ic. Also using a theoretical dtsi called "stm32mp21-ddr3-1x8Gbits-1x16bits-800MHz.dtsi" and define "DDR_MEM_SIZE 0x40000000" which is 1GB. So this is conflicting info because i dont see how 1gb ddr3 is poss

Hi,I was wondering if it's planned for the current STEVAL-EVK-U0I board to work with the 5 Mp VD5943 and VD1943 Image Sensors when they're launched in spring 2026 or if a new USB interface board is planned for evaluation of VD5943 and VD1943?The page for the STEVAL-EVK-U0Ihttps://www.st.com/en/evaluation-tools/steval-evk-u0i.htmlsays "CAM-56G3, CAM-66GY, CAM-55G0, CAM-55G1" so I wasn't sure if it was planned to for it to support evaluation of the VD5943 and VD1943 as well. Will 

Hello Community For some reason, my post from yesterday did not go through and was marked as spam. I'm not interested in moaning about it right now, as I have managed to brick my custom board, designed with STM32H743XI and would be more interested in finding a way to unbrick it. Before jumping to any conclusion, please read the post as it contains crucial info and things I have already tried, which you would like to suggest. Some info about my setup, as mentioned earlier, it's a custom board with BOOT0 and RESET pins exposed using a switch, and there is a JTAG interface for debugging purposes, along with a SEGGER JLink. The way I managed to brick is that I accidentally pulled the RESET line while flashing a FW using Jlink, and since then, it seems memory is in locked mode, and neither Jlink nor ST-vLink is helpful in the rescue mission. Things I have already tried and did not work... maybe I am missing something. I have been in this situation before, and was able to recover from it us

Hello,I start testing with the STEVAL-M25R16B Board and use this Time the self compiled Demo from ST to test it. All works find.Then i made an own PCB with Reader IC  and Antenna on it and connect it to your MCU /Display Board.The Board is connected to 3.3V, GND and the SPI / IRQ Lines. The Antenna on my PCB is very small, only 21x26mm. Inductance measured with Siglent VNA 770nH.( 0.5mm Track Width, 0.3mm Distance, 3 Turns) The from your Tools calculated Values and my final Values after tuning differ..My Result: L=270nH, Cemv 680pF, Cs 220pF, CTune 430pF, Rs 0.68R I tuned the Circuit using my VNA and get a Reading Distance of about 25mm for 14443 Keyfobs and Cardsand about 6cm for ISO15693 Card.This all works fine.  Smith Chart looks perfect.The Rx Voltage is about 1.5Vpp. The Voltage Divider Capacitors are 33p/120p.ST25RProblem: Tags are working but in Emulate Mode i got no Reaction. With the Original Antenna (66x66mm) all is fine.Need a little help

I'm seeing a filesystem corruption issue on an STM32H7 when using FatFs with SDMMC DMA. Hardware / Software STM32H7 SDMMC1 DMA (and MDMA support enabled) FatFs generated by CubeMX D-Cache enabled 8 GB Swissbit industrial SD card Generated sd_diskio.c based on: /* Note: code generation based on sd_diskio_dma_rtos_template_bspv1.c v2.1.4 */ ProblemsThe SD card works normally while mounted: Files can be created Data can be written Data can be read back f_write(), f_sync(), and f_close() all return success However, after: Removing and reinserting the SD card, or Power cycling the system the SD card is detected by Windows as:RAW / Unformattedand must be reformatted before it can be used again.Important observationIf I only perform read operations:Mount cardRead filesPower cycle / reinsert cardthe filesystem remains valid. The corruption only occurs after write operations.Initial investigationBecause the STM32H7 uses D-Cache, I initially suspected cache coherency issues.I

Can you open source your STLINK-V3MINIE?  All hardware and codes,  Your design is not easy to use.

When configuring multiple FDCAN instances in CubeMx, the clock divider settings are not synchronised and are generated twice. For me, FDCAN1 clock divider has the drop down box with multiple options.FDCAN2 only has the "Divide kernel clock by 1" option. This should match FDCAN1 as one common clock divider value. "The clock is common to all FDCAN instances. This parameter is applied only at initialisation of first FDCAN instance." from UM2570.The first issue is within CubeMx, this clock divider value is then used for the indicator calculations:- Nominal Time Quantum- Nominal Time for One Bit- Nominal Baud RateIf the clock values are wrong, these values will be wrong.Second issue is the Init.ClockDivider code is generated twice, one per instance instead of just once.If these values are the same, there'll be no issue. If different then the latter will overwrite the former. In main.c MX_FDCAN1_Init(); MX_FDCAN2_Init(); in fdcan.c void MX_FDCAN1_Init(void) { /* USER CODE END FDCAN1_Init 1

As I understand, the TSSOP20 version needs an external oscillator instead of a 8MHz crystal connected directly to the MCU pins. Is that correct?I'm asking because I have seen a board on AliExpress using this same processor with a 8MHz crystal.

I am currently using TouchGFX to develop a project. How can I independently control GPU2D to draw graphics on a dynamic bitmap without affecting the TouchGFX display? I have already obtained the NeoChromSDK, but the examples in the NeoChromSDK all use GPU2D independently as well.  I can draw with GPU2D if touchgfx not in use,But once I display them both, screen got glitched.

Why, oh why have you separated IDE and MX such that .ioc files can no longer be opened in IDE?I cannot imagine any benefits and it makes the IDE significantly worse, such that I've felt compelled to revert to version 1.19.0 ( go to Help -> About STM32CubeIDE -> Installation Details -> Installation History -> select version -> Revert)I couldn't find any other means of feeding back my strong dislike of this change other than a post like this. I hope version 2.1.0 comes out soon and re-integrates MX and IDE!

Just for fun...i tried to use the SPI on H743 by direct setting and writing to registers:- i never got it working on some attempts years ago, so just used HAL , which just works.- now i tried again: cannot be, its so difficult...- ok, its a over complicated construction....old SPI on F303 works instantly and fast, no problem there.- but now have AI ... can it help?So i tried Sidekick, it should be easy for him...it...whatever...I asked how to do...in German, more easy for me - and a test: can it understand...?Sidekick tells:3. ZusammenfassungUm auf dem STM32H743 einen SPI-Transfer durch Schreiben auf SPI_TXDR zu starten, müssen Sie:Die Datenlänge im SPI_CFG1-Register korrekt einstellen,die Bitreihenfolge im SPI_CFG2-Register wählen,die relevanten GPIOs konfigurieren,das SPI-Modul aktivieren,und dann die Daten in der konfigurierten Länge auf SPI_TXDR schreiben.Ein Schreibzugriff mit weniger als der konfigurierten Datenlänge ist nicht zulässig.--- THIS didnt help me, as it also just brin

HelloI have custom PCB with STM32G491KE connected to an LSM6SV80X IMU directly via SPI. I'm having an issue with not being able to receive any data from the IMU, the the read value is always 0xFF which I've read is usually an issue with the slave/subnode/agent device not responding. Here's how the SPI interface is configured (via CubeMX with X-CUBE-MEMS1)__weak HAL_StatusTypeDef MX_SPI1_Init(SPI_HandleTypeDef* hspi) { HAL_StatusTypeDef ret = HAL_OK; hspi->Instance = SPI1; hspi->Init.Mode = SPI_MODE_MASTER; hspi->Init.Direction = SPI_DIRECTION_2LINES; hspi->Init.DataSize = SPI_DATASIZE_8BIT; hspi->Init.CLKPolarity = SPI_POLARITY_LOW; hspi->Init.CLKPhase = SPI_PHASE_1EDGE; hspi->Init.NSS = SPI_NSS_SOFT; hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; hspi->Init.FirstBit = SPI_FIRSTBIT_MSB; hspi->Init.TIMode = SPI_TIMODE_DISABLE; hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; hspi->Init.CRCPolynomial = 7; hspi->In

So I'd been merrily using STM32CubeIDE all morning, doing the usual code-download-debug cycle with no problems at all.Then, after some code updates & successful build, it suddenly can't reach the GDB server: STMicroelectronics ST-LINK GDB server. Version 7.4.0Copyright (c) 2023, STMicroelectronics. All rights reserved.Starting server with the following options: Persistent Mode : Disabled Logging Level : 1 Listen Port Number : 61234 Status Refresh Delay : 15s Verbose Mode : Disabled SWD Debug : Enabled InitWhile : EnabledFailed to bind to port 61234, error code -1: No errorFailure starting GDB server: TCP port 61234 not available.Shutting down...Exit. Several people seem to have had this recently; eg,https://community.st.com/t5/stm32cubeide-mcus/cubeide-1-18-cannot-detect-st-link-anymore/m-p/784313?search-action-id=49992011530&search-result-uid=784313https://community.st.com/t5/stm32cubeide-mcus/st-link-error-failed-to-bind-to-port-61235-failure-starting-swv/m-p/784642

This might be my misunderstanding of how OVERRIDES work, but I'm building with the recently-released "wrynose_v26.02.18" branch of meta-st-stm32mp and, for the purpose of debugging, I wanted to set:ST_OPTEE_CORE_DEBUG = "y"so I did that in my local.conf file, but after I set it, it still had the value of "n" for the build, so I dumped the value to see how it was (or was not) being set:bitbake-getvar -r optee-os-stm32mp ST_OPTEE_CORE_DEBUG... snip ...# $ST_OPTEE_CORE_DEBUG [3 operations]# set /home/rpjday/BOARDS/nexus/wrynose/build/conf/local.conf:13# "y"# set /home/rpjday/Layers/wrynose/st/meta-st-stm32mp/recipes-security/optee/optee-os-stm32mp-common.inc:37# [_defaultval] "y"# override[stm32mp15common]:set? /home/rpjday/Layers/wrynose/st/meta-st-stm32mp/recipes-security/optee/optee-os-stm32mp-common.inc:38# "n"# pre-expansion value:# "n"ST_OPTEE_CORE_DEBUG="n"You can see how the first line seems to show that I am explicitly setting it in my local.conf, then the processing continues th

G4 ref man says there is 1 (one) FDCAN peripheral:Yet when editing the IOC file I see 2 (two) FDCAN peripherals:I believe the ref man. What's with the IOC file editor?

I am trying to use the LIS2DUX12 on the STEVAL- MKI109D and use MEMS studio to merge a MLC config I developed and an example FSM config. I have the merged file, but how do I run/test the config onto the board and see if it works?

Hi All,  In my application, I am using the STM32L451RCT6 and trying to configure COMP2 with the internal Vref as a reference (specifically 3/4 Vref). For some reason, it never worked. I was only able to get it working when using DAC_CH1 or an external source as the reference. After a few days of troubleshooting and research, I finally found a relevant block diagram along with an important note in the reference manual (page 532). The thing is, there are no mentions or explanations of this behavior in the reference manual, datasheet, or errata other than this. Could you confirm whether the STM32L45x series actually supports using the internal Vref as a comparator reference or am I facing some other issue here? Thank you!   

I am using the Analog Devices EVAL-ADE9430 Evaluation board for testing one of their devices. The Evaluation board uses the NUCLEO-144 STM32F413ZH processor. I am using the Keil uVision development setup to run and debug code.  I am specifically concentrating on the SPI Bus Driver and the timing. I have no previous experience with STM Devices and how the SPI transfers happen in the processor. so I apologize a head of time. The Analog Devices ADE9430 uses a a 16-bit CRC (CRC-16-CCITT) and from what I originally read  the STM32F413ZH processor supports 32-Bit CRC (CRC-32-CCITT).  Diving deeper into the NUCLEO-144 STM32F413ZH processor manual section "29.4.2 CRC calculation" indicates "The SPI offers CRC8 or CRC16 calculation depending on the data format selected through the DFF bit." When the DFF bit (SPI_CR1 bit 11) is 0 it uses CRC8, when the DFF bit is '1' it uses CRC16.https://www.st.com/resource/en/reference_manual/rm0430-s

Hello,the STM32G474RBTx CubeMX Clock Configuration ADC1_2 and ADC3_4_5 are swapped - the ADC1_2 Mux is actually referring to the ADC3_4_5 Mux, at least when it comes to the subsequent divider options in the respective ADC configurations.Setting ADC12 Mux to PLLP with e.g. 48.57 MHz allows me to put ADC3_4_5 into ASYNC_DIV_1, whereas the ADC3_4_5 Clock Mux is set to SYSCLK with 170MHz. ADC12 cannot use ASYNC_DIV_1 or 2, even though they should be able to.It also happens the other way around.I am using CubeMX 6.17.0 with the G4 package version 1.6.3