Solved

I use STM32CubeIDE on Linux Ubuntu (and to a lesser extent on MacOS and Windows, but I don't recall having a problem on the last 2 operating systems). About once or twice a day, at random, several of the keys such as <backspace> and <enter> and <delete> stop working. All the alphabetical and number keys work as normal. If I switch to a different application all the keys are working, but when I switch back to Cube the problem continues.I solve the problem by saving my work, shutting and relaunching Cube. Is this a bug in the application?

Hello,   ich set up my project with CubeMX for a CAN-FD (1 MBit/s / 4,8 MBit/s) and a Display for communication. Now i have the problem, that the SCK Signal for the communication looks more like a sawtooth signal than a rectangle. Also the SPI-Prescaler for the baud rate does not affect this signal. i am really confused. I need to use the 48 MHz HSE for my 4,8 MBit/s data phase for CAN-FD. I use an NUCLEO-C092RC and a LCD Display with ILI9341 (library from Mauro De Vecchi) Thanks for the help

Hello. Please check if there are any issues with the settings as shown below. PB4 : SPI1_miso PB3 : SPI1_sck PD6 : SPI1_mosi   Thank you.

Original post: https://community.st.com/t5/stm32-mcus-products/stm32h7-flash-crc/td-p/887279 Github: https://github.com/STMicroelectronics/stm32h7xx-hal-driver/blob/1501be883dae6f202c1d3f856ee6b11407dc257d/Src/stm32h7xx_hal_flash_ex.c#L733 HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result) { ... ... FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC; ... ... }​|= will not program the expected burst size if the reset value is not b00. It looks like on reset the value is b01 (16 flash words). So if user try to set to burst size of 4 flash words (b00) it'll remain set to b01.

 Hi all,I have a board designed around the STM32MP153FAD (TFBGA257, 10×10 mm, 0.5/0.65 mm pitch, 257 balls). Since the MP153 does not include a DSI controller or GPU, I did not connect any DSI-related power pins or signals. Due to stock shortages, I am now considering switching to the STM32MP157FAD, which shares the same TFBGA257 footprint.My question is: can the STM32MP157FAD be used on this board without connecting the DSI-specific power rails?The DSI power pins that exist on the MP157 but were not populated on my design are:VDD_DSI — DSI I/O supplyVDD1V2_DSI_REG — output of internal 1.2 V DSI regulatorVDD1V2_DSI_PHY — 1.2 V supply for DSI PHYVDDA1V8_DSI — 1.8 V analog supply for DSIMy concern is whether the MP157 will operate correctly (for non-DSI use cases) if these pins receive no supply. (Unused pins are floating right now, is that correct or should I connect it to GND)I have attached my current schematic for reference.Any guidance would be appreciated.Best regardsRegards

I'm using STM32CubeMX 6.17.0 with NUCLEO-U575ZI-Q, it generated the following code:/* Initialize COM1 port (115200, 8 bits (7-bit data + 1 stop bit), no parity */ BspCOMInit.BaudRate = 115200; BspCOMInit.WordLength = COM_WORDLENGTH_8B; BspCOMInit.StopBits = COM_STOPBITS_1; BspCOMInit.Parity = COM_PARITY_NONE; BspCOMInit.HwFlowCtl = COM_HWCONTROL_NONE;The comment is wrong, the UART has 8 bits of data instead of 7 bits.

I am running the Analog Devices EVAL-ADE9430 board and noticed if I enable CRC checking reading 32 bit registers fail while 16-bit registers always pass. I trace it down to the  AFERead16BitBuffer() function not returning a status after reading the register over the SPI bus. This allows 16 bit register reads to work all the time while 32 Bit registers fail all the time (that's another story).   See line 12 below:     HAL_SPI_Receive(&hSPI, (uint8_t *)&pData[0], 2 * numSamples, SPI_TIMEOUT); uint32_t AFERead16BitBuffer(uint16_t addr, uint16_t numSamples, uint16_t *pData) { int32_t status = SYS_STATUS_SUCCESS; cmdBuffer[0] = (addr >> 4); cmdBuffer[1] = ((addr & 0x0F) << 4) + 8; HAL_GPIO_WritePin(GPIOD, GPIO_PIN_14, GPIO_PIN_RESET); status = HAL_SPI_Transmit(&hSPI, (uint8_t *)&cmdBuffer, 2, SPI_TIMEOUT); if (status == 0) { HAL_SPI_Receive(&hSPI, (uint8_t *)&pData[0], 2 * numSamples, SPI_TIMEOUT); } HAL_GPI

Hello, I wrote a project maybe 2 weeks ago, at that time, everything was ok.  then i used stlink to download and debug the code yesterday, at first time, it worked ok, but later, i did download and debug again with stlink. it cannot work. the log as below.my setting as below:so what is the problem? how to fix it?thanks. 

 Hi everyone,I wanted to share a project I’ve been building over the last few years. It’s called Mk, an operating system built entirely from scratch for the STM32F746G-DISCO and STM32F746G-Eval2 boards.These boards are powered by an ARM Cortex-M7 running at 216MHz. Initially, my goal was just to implement a small scheduler, but I stacked layers one after another to make it as complete as possible. Currently, I think I've added enough layers to claim it as a functional, lightweight OS.Mk features:A KernelPreemptive, priority-based multitasking scheduler (fixed-priority, O(1) selection via hardware CLZ instruction) Trusted Execution Environment (TEE) using the Cortex-M7 MPU (privileged and unprivileged mode isolation) Synchronization primitives: mutex, semaphore, event flags, mailbox Fixed-size memory pools Synchronous and asynchronous callback execution systemA Dynamic ELF Loader Mk can load and execute external .elf binaries at runtime, relocated dynamically into 64 KB pages of the ext

Hello,   I am working on I3C private transfers. When I build the context buffer with HAL_I3C_CTRL_BuildTransferCtxPrivate I get an assert when IS_I3C_PRIVATE_MODE is checked against HAL_I3C_PRIVATE_WITH_ARB_RESTART. Is the exclusion of HAL_I3C_PRIVATE_WITH_ARB_RESTART from the macro below intentional? stm32c5xx_hal_i3c.c: line 574 #define IS_I3C_PRIVATE_MODE(MODE) (((MODE) == HAL_I3C_PRIVATE_WITH_ARB_STOP) \ || ((MODE) == HAL_I3C_PRIVATE_WITHOUT_ARB_RESTART) \ || ((MODE) == HAL_I3C_PRIVATE_WITHOUT_ARB_STOP) \ || ((MODE) == HAL_I2C_PRIVATE_WITH_ARB_RESTART) \ || ((MODE) == HAL_I2C_PRIVATE_WITH_ARB_STOP) \ || ((MODE) == HAL_I2C_PRIVATE_WITHOUT_ARB_RESTART) \ || ((MODE) == HAL_I2C_PRIVATE_WITHOUT_ARB_STOP))  Thank you, -Gil

Hello, I am looking for an example of how to use private I3C transfers for STM32C562RE. I read the I3C examples posted on Github but I did not find any controller or target examples that use HAL_I3C_CTRL_Transfer_DMA and HAL_I3C_TGT_Receive_DMA for private transfers using HAL2. Your help would be appreciated,Gil

Recently, I was trying to implement SDMMC+DMA+SDFAT to read and write the SD card of my Class on the STM32H750VBT6. Then I found that the DMA of SDMMC was gone. I saw some online materials saying that MDMA needs to be configured, and some also said that SDMMC does not need to configure DMA as it has its own independent IDMA bus. What is the actual situation when it is directly mounted on AHB? Are there any configuration screenshots and programs of CubeMX for SDMMC+DMA? I'd like to refer to it. Thank you!

Does the ST67W611M1  (-B version) with PCB antenna have a built in rf switch? We want to programmatically or via pins switch between the PCB antenna and an external antenna.

Dear. AllI'm asking how to use STemWin on stm32h743 mcu.How to add STemWin on STM32CubeIDE? (Current Use Version. 1.13.0)?How can I run a project with the development board I bought? (STM32H743I-EVAL)?In particular, I want to run the STemWin_SampleDemo project.I`m use IAR EWARM ver 9.xx but in stm32cubeh7-v1-12-1 andSTM32Cube_FW_H7_V1.11.0\Repository\STM32Cube_FW_H7_V1.11.0\Projects\STM32H743I-EVAL\Demonstrations\STemWini find STemWin.ewp project which use OGLastSavedByProductVersion 8.20.2.14834.It mean`s STemWin.ewp should compile on EWARM 8.20 or late.Is it possible to use example on later version EWARM ?Best regards.

Hello everyone：On touchgfx support website:https://support.touchgfx.com/docs/development/scenarios/touchgfx-on-gpu2d ,there is a demo of map using NeoChromVG,this is the demo videoSo,where can I get this demo project?

I wonder why this is happening after U-boot has booten up?It seems that something is NULL. D/TC:? 0 tee_ta_close_session:484 Destroy session Error: eth1@482c0000 address not set. D/TC:? 0 tee_ta_init_session_with_context:562 Re-open trusted service a8cfe406-d4f5-4a2e-9f8d-a25dc754c099 F/TC:? 0 pta_scmi_invoke_command:404 SCMI command 0x3 ptypes 0x3 F/TC:? 0 pta_scmi_invoke_command:404 SCMI command 0x4 ptypes 0x651 D/TC:? 0 tee_ta_close_session:465 csess 0x821301f0 id 1 D/TC:? 0 tee_ta_close_session:484 Destroy session No ethernet found. �7�[r�[999;999H�[6n�8No EFI system partition No EFI system partition Failed to persist EFI variables D/TC:? 0 tee_ta_init_pseudo_ta_session:303 Lookup pseudo TA ab7a617c-b8e7-4d8f-8301-d09b61036b64 D/TC:? 0 tee_ta_init_pseudo_ta_session:315 Open rng.pta D/TC:? 0 tee_ta_init_pseudo_ta_session:330 rng.pta : ab7a617c-b8e7-4d8f-8301-d09b61036b64 F/TC:? 0 plat_prng_add_jitter_entropy:74 0x1C D/TC:? 0 tee_ta_close_session:465 csess 0x821301f0 id 1 D/TC

Hi everyone,I am encountering a HCI_HARDWARE_ERROR_EVENT with code 0x02 (BlueCore time overrun error) on STM32WB devices.Key observations:Issue is observed only on some units, while others operate normallyAll devices use the same firmware, BLE stack, and FUS versionsAffected units show unstable BLE behavior (disconnects or degraded performance)Validation performed:Tested with STM32 reference example (BLE_p2pServer)The issue is still reproduciblePCB layout and hardware design have been reviewed and validatedNo application-specific changes involved during testingQuestions:Root causeWhat typically triggers a BlueCore time overrun at the controller level?Does this point more toward hardware timing issues (clock accuracy, RF timing), or internal controller or stack conditions?Unit variationHas anyone observed this error occurring only on a subset of devices?Could this be related to component tolerances (HSE or LSE oscillator, RF matching network, power stability, etc.)?Failure diagnosisWhat

What does the appearance of KF50BD-TR look like ? Does it have pin 1 marker?Can you provide the relevant drawings?

Hi, I'm using the STM32C071K8U6's built-in USB DFU bootloader for one-time production programming. After flashing, PA11/PA12 (USB D+/D-) are used as regular GPIO outputs to control two P-MOSFETs (each with their 100kΩ gate pull-ups to 4.2V).   The USB functionality is not used by the end customer, but the USB connector remains accessible for charging. This means a PC's USB cable may be connected during normal use allowing for potential signal injected into those traces resulting into the PMOS being turned on/off by the PC if it detects there is a USB device connected and tries to enumerate it.   The two core issues: a) When a user plugs into a PC for charging, we need to guarantee the host does not attempt enumeration, and that nothing the host does on D+/D- interferes with our GPIO-driven MOSFET gates. b) because the PA11 and PA12 traces also go all over the PCB - i.e. they form very long stubs - we need to make sure this does not prevent the USB from working properly d

The STM6905 datasheet says in Table 2 that there is an internal 10k pull-up on RST#, which seems wrong since that's an open-drain output. Then in Section 2.6 and in Section 3 it says that an external pull-up to VCC should be used.

Hello,I would like to ask about the UFQFPN32 package footprint for the STM32G491KEUx device.We are using the following part:Part number: STM32G491KEUxPackage: UFQFPN32While reviewing the datasheet and package information, we found that the actual UFQFPN32 package appears to have an exposed pad (EP) on the bottom side of the package.However, in the datasheet/package information we reviewed, the UFQFPN32 package information and footprint example do not seem to include the EP or the EP land pattern.In particular, the UFQFPN32 package information is shown in the document from page 166 to page 168, but we could not find any information regarding the exposed pad or the recommended PCB land pattern for the EP.Could you please confirm the following?Is the exposed pad information for the STM32G491KEUx UFQFPN32 package omitted from the datasheet/package information?For actual PCB design, should we include an EP land pattern for the UFQFPN32 package?If the EP land pattern should be included, shou

Hi STM teams , i have developed a custom NFC board using the STM32L476RCT6 and the ST25R3916B NFC reader, based on the reference design of STEVAL-D25R16B (https://www.st.com/resource/en/schematic_pack/steval-25r3916b-schematic.pdf). I am using an external sticker antenna (Manufacturer Part Number: V2089-013-A-01). Currently, the board detects only the STEVAL-SMARTAG2 NFC tag card (https://www.st.com/resource/en/schematic_pack/steval-smartag2-schematic.pdf), while other NFC cards are not being detected. However, when I connect the custom NFC board to the DK antenna, it successfully detects the STEVAL-SMARTAG2 card as well as all other NFC cards. so i think issue may be sticker antenna Could anyone suggest a suitable sticker antenna or recommend an alternative external antenna solution? I have attached pictures of the sticker antenna, the STEVAL-SMARTAG2 card, and the other NFC tags for reference.

Product/Tool: STM32CubeProgrammer CLI v2.19.0Target MCU: STM32U385RG-Q (Nucleo-U385RG-Q board)Connection: SWD, mode=UR (Under Reset)TZEN: 0 (non-secure)================================================================================SUMMARY================================================================================We are unable to program a full 16-byte OTP row using STM32_Programmer_CLI.Only the first double-word (8 bytes) of a row can be written. Any attempt toprogram the second double-word of the same row fails silently (word remains0xFFFFFFFF) or is rejected by the flash controller, even though the row shouldnot be locked until both double-words are programmed.Per the reference manual, the OTP lock granularity is one 16-byte row(2 double-words). We expect to be able to program both double-words within arow independently (each in a single operation), provided neither has beenwritten previously. However in practice, programming the first double-wordappears to immediately lock the

this thread is split from this thread hello Last question, I just saw the example but it's not for the STM32H755ZI-Q series, are the examples still compatible with this STM32H755 series? Thanks

I am trying to do multidrop with STM32WL5MOC and STM32U031. I have some issues:[1] When WL5MOC is the only active MCU in the circuit (U0 is not powered on) I cannot connect M4 core using TargetSel=0x04970041 option:I can connect to M0+ core using tagetsel (STM32_Programmer_CLI -c port=swd TargetSel=0x04970041 ap=1 mode=hotplug)If I try the same with ap=0, CLI cannot connect to M4 core and retires with ap=1 and then connects M0+ core againThere is no issue when not using targetsel option and U0 is disconnected. I can connect both WL5 cores with ap=0 and ap=1 options.[2] If I power on U0 and try multidrop, I cannot connect any of the cores of WL5:I can connect U0 with targetsel option(STM32_Programmer_CLI -c port=swd TargetSel=0x04590041 ap=0 mode=hotplug).. At first CLI cannot connect with ap=0 and retries with ap=1 and then connects.Interestginly If I try ap=1 directly, it cannot connect to U0 (STM32_Programmer_CLI -c port=swd TargetSel=0x04590041 ap=0 mode=hotplug)Am I missi