CAN-Bus no callback/received frame; FDCAN STM32G474

Can you show the "when I try to receive a CAN-Frame" part of your code? What does your callback function look like?

Hello,

as far as I'm aware the Function "HAL_FDCAN_RxFifo0Callback" needs to be implemented, which I did, I set a breakpoint, but it is never involked. "HAL_FDCAN_IRQHandler" is also never invoked.

void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *phfdcan, uint32_t RxFifo0ITs)
{
 if((RxFifo0ITs & FDCAN_IT_RX_FIFO0_NEW_MESSAGE) != RESET)
 {
 /* Retrieve Rx messages from RX FIFO0 */
 if (HAL_FDCAN_GetRxMessage(phfdcan, FDCAN_RX_FIFO0, &RxHeader, RxData) != HAL_OK)
 {
 Error_Handler();
 }
 else
 {
 // HAL_Ok
 if ((RxHeader.DataLength == CanMsgLen_Pressure)&&(RxHeader.Identifier == CanMsgId_Control))
 {
 canSendData = RxData[0U];
 }
 
 }
 
 }
}

Best Regards, Seppel

That looks about right.

How about your receive buffers configuration?

Can you copy-paste the FDCAN_InitTypeDef structure declaration that was generated?

I mean this guy:

typedef struct
{
 uint32_t FrameFormat; /*!< Specifies the FDCAN frame format.
 This parameter can be a value of @ref FDCAN_frame_format */
 
 uint32_t Mode; /*!< Specifies the FDCAN mode.
 This parameter can be a value of @ref FDCAN_operating_mode */
 
 FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode.
 This parameter can be set to ENABLE or DISABLE */
 
 FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature.
 This parameter can be set to ENABLE or DISABLE */
 
 FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling.
 This parameter can be set to ENABLE or DISABLE */
 
 uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is
 divided for generating the nominal bit time quanta.
 This parameter must be a number between 1 and 512 */
 
 uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN
 hardware is allowed to lengthen or shorten a bit to perform
 resynchronization.
 This parameter must be a number between 1 and 128 */
 
 uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
 This parameter must be a number between 2 and 256 */
 
 uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
 This parameter must be a number between 2 and 128 */
 
 uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is
 divided for generating the data bit time quanta.
 This parameter must be a number between 1 and 32 */
 
 uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN
 hardware is allowed to lengthen or shorten a data bit to
 perform resynchronization.
 This parameter must be a number between 1 and 16 */
 
 uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1.
 This parameter must be a number between 1 and 32 */
 
 uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2.
 This parameter must be a number between 1 and 16 */
 
 uint32_t MessageRAMOffset; /*!< Specifies the message RAM start address.
 This parameter must be a number between 0 and 2560 */
 
 uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters.
 This parameter must be a number between 0 and 128 */
 
 uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters.
 This parameter must be a number between 0 and 64 */
 
 uint32_t RxFifo0ElmtsNbr; /*!< Specifies the number of Rx FIFO0 Elements.
 This parameter must be a number between 0 and 64 */
 
 uint32_t RxFifo0ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 0 element.
 This parameter can be a value of @ref FDCAN_data_field_size */
 
 uint32_t RxFifo1ElmtsNbr; /*!< Specifies the number of Rx FIFO 1 Elements.
 This parameter must be a number between 0 and 64 */
 
 uint32_t RxFifo1ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 1 element.
 This parameter can be a value of @ref FDCAN_data_field_size */
 
 uint32_t RxBuffersNbr; /*!< Specifies the number of Dedicated Rx Buffer elements.
 This parameter must be a number between 0 and 64 */
 
 uint32_t RxBufferSize; /*!< Specifies the Data Field Size in an Rx Buffer element.
 This parameter can be a value of @ref FDCAN_data_field_size */
 
 uint32_t TxEventsNbr; /*!< Specifies the number of Tx Event FIFO elements.
 This parameter must be a number between 0 and 32 */
 
 uint32_t TxBuffersNbr; /*!< Specifies the number of Dedicated Tx Buffers.
 This parameter must be a number between 0 and 32 */
 
 uint32_t TxFifoQueueElmtsNbr; /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue.
 This parameter must be a number between 0 and 32 */
 
 uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection.
 This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
 
 uint32_t TxElmtSize; /*!< Specifies the Data Field Size in a Tx Element.
 This parameter can be a value of @ref FDCAN_data_field_size */
 
} FDCAN_InitTypeDef;

I don't know how similar G4 / H7 FDCANs are, so all of the following might only apply to the H7.

The H7 has some 10 kB SRAM reserved for FDCAN.

This "CAN-RAM" is used for:

• filter settings
• RX & TX buffers and FIFOs

The RAM layout depends on your INIT settings, how many filters, buffers, etcpp you assign.

Then it calculates the RAM (starting) addresses / pointers from that.

First thing I see in your init:

StdFiltersNbr = 0; ExtFiltersNbr = 0;

Which means you have no filters assigned to memory.

Comparing to my H7 source, I also miss the settings for RX & TX buffers & FIFO, so my H7 init looks like this:

void MX_FDCAN1_Init(uint32_t u32DataRate)
{
	FDCAN_HandleTypeDef *phCan = &hCan1;
	FDCAN_FilterTypeDef sFilterConfig = { 0 };
 
	phCan->Instance = FDCAN1;
 
	phCan->Init.FrameFormat 			= FDCAN_FRAME_FD_BRS;
	phCan->Init.Mode 					= FDCAN_MODE_NORMAL;//FDCAN_MODE_EXTERNAL_LOOPBACK;//
	phCan->Init.AutoRetransmission 		= ENABLE;
	phCan->Init.TransmitPause 			= ENABLE;
	phCan->Init.ProtocolException 		= ENABLE;
 
/* clock / timing */
 
/* nominal = arbitration phase
 *	NBTP
 * 	80 MHz: tq = NominalPrescaler x (1/fdcan_ker_ck)
 *		-> tq = 12.5 ns
 *	data rate = 1 / ((SyncSeg + Seg1 + Seg2) * tq)
 *		with SyncSeg = 1
 *	0.5 Mbps = 160 * tq
 *		-> TimeSeg1 + TimeSeg2 = 157
 */
	phCan->Init.NominalPrescaler 		= 1;		/* tq = NominalPrescaler x (1/fdcan_ker_ck) */
#if( 1 )
/* 5000 ppm */
	phCan->Init.NominalTimeSeg1 		= 138;		/* NTSEG1 1..256, NominalTimeSeg1 = Propagation_segment + Phase_segment_1 */
	phCan->Init.NominalTimeSeg2 		= 21;		/* NTSEG2 1..128 */
	phCan->Init.NominalSyncJumpWidth 	= 20;		/* NSJW 1..128 should be < NTSEG2 */
#else
/* 500 ppm */
	phCan->Init.NominalTimeSeg1 		= 155;		/* NTSEG1 1..256, NominalTimeSeg1 = Propagation_segment + Phase_segment_1 */
	phCan->Init.NominalTimeSeg2 		= 4; 		/* NTSEG2 1..128 */
	phCan->Init.NominalSyncJumpWidth 	= 3; 		/* NSJW 1..128 should be < NTSEG2 */
#endif
 
/* data = data phase with bit rate switching
 *	DBTP
 * 	80 MHz: tq = DataPrescaler x (1/fdcan_ker_ck)
 *		-> tq = 12.5 ns
 *	data rate = 1 / ((SyncSeg + Seg1 + Seg2) * tq)
 *		with SyncSeg = 1
 */
	phCan->Init.DataPrescaler 			= 1;		/* DBRP 1..32 */
 
	CanInitBsrDataRate(phCan, u32DataRate);
 
/* RAM: filters, buffers */
	/* start pos in RAM of 2560 32-bit words */
	phCan->Init.MessageRAMOffset 		= 0;
 
	phCan->Init.StdFiltersNbr 			= 16;
	phCan->Init.ExtFiltersNbr 			= 16;
 
	phCan->Init.RxFifo0ElmtsNbr 		= 16;
	phCan->Init.RxFifo0ElmtSize 		= FDCAN_DATA_BYTES_64;
 
	phCan->Init.RxFifo1ElmtsNbr 		= 16;
	phCan->Init.RxFifo1ElmtSize 		= FDCAN_DATA_BYTES_64;
 
	phCan->Init.RxBuffersNbr 			= 16;
	phCan->Init.RxBufferSize 			= FDCAN_DATA_BYTES_64;
 
	phCan->Init.TxEventsNbr 			= 0;
	phCan->Init.TxBuffersNbr 			= 4;
	phCan->Init.TxFifoQueueElmtsNbr 	= 4;
	phCan->Init.TxFifoQueueMode 		= FDCAN_TX_FIFO_OPERATION;
	phCan->Init.TxElmtSize 				= FDCAN_DATA_BYTES_64;
 
	if( HAL_FDCAN_Init(phCan) != HAL_OK ) Error_Handler_FL(__FILE__, __LINE__);
 
/* Filters - STANDARD */
	sFilterConfig.FilterType 		= 0;	/* ignored for FDCAN_FILTER_TO_RXBUFFER */
	sFilterConfig.FilterID2 		= 0;	/* ignored for FDCAN_FILTER_TO_RXBUFFER */
 
	/* Configure standard ID reception filter to Rx buffer 0 */
	sFilterConfig.IdType 			= FDCAN_STANDARD_ID;
	sFilterConfig.FilterIndex 		= 0;
	sFilterConfig.FilterConfig 		= FDCAN_FILTER_TO_RXBUFFER;
	sFilterConfig.RxBufferIndex 	= 0;								/* store ID1 to this RX buffer */
	sFilterConfig.FilterID1 		= CAN_FILTER_STD_TEST_RXB_ID1;		/* MessageID and FilterID1 must match exactly */
	HAL_FDCAN_ConfigFilter(phCan, &sFilterConfig);
 
	/* Configure standard ID reception filter to Rx buffer 1 */
	sFilterConfig.IdType 			= FDCAN_STANDARD_ID;
	sFilterConfig.FilterIndex 		= 1;
	sFilterConfig.FilterConfig 		= FDCAN_FILTER_TO_RXBUFFER;
	sFilterConfig.RxBufferIndex 	= 1;							/* store ID1 to this RX buffer */
	sFilterConfig.FilterID1 		= CAN_FILTER_STD_TEST_RXB_ID2;		/* MessageID and FilterID1 must match exactly */
	HAL_FDCAN_ConfigFilter(phCan, &sFilterConfig);
 
	/* Configure standard ID reception filter to Rx buffer 2 */
	sFilterConfig.IdType 			= FDCAN_STANDARD_ID;
	sFilterConfig.FilterIndex 		= 2;
	sFilterConfig.FilterConfig 		= FDCAN_FILTER_TO_RXBUFFER;
	sFilterConfig.RxBufferIndex 	= 2;							/* store ID1 to this RX buffer */
	sFilterConfig.FilterID1 		= CAN_FILTER_STD_TEST_RXB_ID3;		/* MessageID and FilterID1 must match exactly */
	HAL_FDCAN_ConfigFilter(phCan, &sFilterConfig);
 
	/* Configure standard ID reception filter to Rx buffer 3 */
	sFilterConfig.IdType 			= FDCAN_STANDARD_ID;
	sFilterConfig.FilterIndex 		= 3;
	sFilterConfig.FilterConfig 		= FDCAN_FILTER_TO_RXBUFFER;
	sFilterConfig.RxBufferIndex 	= 3;							/* store ID1 to this RX buffer */
	sFilterConfig.FilterID1 		= CAN_FILTER_STD_TEST_RXB_ID4;		/* MessageID and FilterID1 must match exactly */
	HAL_FDCAN_ConfigFilter(phCan, &sFilterConfig);
 
/* Filters - EXTENDED */
	sFilterConfig.RxBufferIndex 	= 0;	/* ignored if not FDCAN_FILTER_TO_RXBUFFER */
 
	/* Configure extended ID reception filter to Rx FIFO 0 */
	sFilterConfig.IdType 			= FDCAN_EXTENDED_ID;
	sFilterConfig.FilterIndex 		= 0;
	sFilterConfig.FilterType 		= FDCAN_FILTER_RANGE_NO_EIDM;	/* Range from FilterID1 to FilterID2, no EIDM mask */
	sFilterConfig.FilterConfig 		= FDCAN_FILTER_TO_RXFIFO0;
	sFilterConfig.FilterID1 		= CAN_FILTER_EXT_TEST_RXF_ID1;
	sFilterConfig.FilterID2 		= CAN_FILTER_EXT_TEST_RXF_ID2;
	HAL_FDCAN_ConfigFilter(phCan, &sFilterConfig);
 
	/* Configure extended ID reception filter to Rx FIFO 1 */
	sFilterConfig.IdType 			= FDCAN_EXTENDED_ID;
	sFilterConfig.FilterIndex 		= 1;
	sFilterConfig.FilterType 		= FDCAN_FILTER_RANGE_NO_EIDM;	/* Range from FilterID1 to FilterID2, no EIDM mask */
	sFilterConfig.FilterConfig 		= FDCAN_FILTER_TO_RXFIFO1;
	sFilterConfig.FilterID1 		= CAN_FILTER_EXT_TEST_RXF_ID3;
	sFilterConfig.FilterID2 		= CAN_FILTER_EXT_TEST_RXF_ID4;
	HAL_FDCAN_ConfigFilter(phCan, &sFilterConfig);
 
	/* Configure global filter to reject all non-matching frames */
	HAL_FDCAN_ConfigGlobalFilter(phCan, FDCAN_REJECT, FDCAN_REJECT, FDCAN_REJECT_REMOTE, FDCAN_REJECT_REMOTE);
 
#if( 0 )
	/* Configure Rx FIFO 0 watermark to 2 */
	HAL_FDCAN_ConfigFifoWatermark(phCan, FDCAN_CFG_RX_FIFO0, 2);
 
	/* Activate Rx FIFO 0 watermark notification */
	HAL_FDCAN_ActivateNotification(phCan, FDCAN_IT_RX_FIFO0_WATERMARK, 0);
#endif
 
	/* timestamp enable, bit time, no prescaler */
	phCan->Instance->TSCC = 1;
 
/* enable TDC = transmitter delay compensation
 *	this is a MUST for high data rates
 */
	/* configure Tx Delay Compensation : TdcOffset = DataTimeSeg1 * DataPrescaler */
	uint32_t u32TdcOffs = ((uint32_t)phCan->Instance->DBTP >> FDCAN_DBTP_DTSEG1_Pos) + 1;
	uint32_t u32TdcFltWdw = 0;
 
	/* set TDC filter window */
	phCan->Instance->TDCR = (u32TdcFltWdw << FDCAN_TDCR_TDCF_Pos);
	/* set TDC offset */
	phCan->Instance->TDCR |= (u32TdcOffs << FDCAN_TDCR_TDCO_Pos);
	/* enable TDC */
	phCan->Instance->DBTP |= FDCAN_DBTP_TDC;
 
/* start FDCAN */
	HAL_FDCAN_Start(phCan);
}
 

Don't forget that CubeMX is just a basic setup-thingy.

So use the debugger or the UART to check register settings, like interrupt enable, memory addresses, ...

I just see that I had to put some interrupt enables in the MSP init with direct register settings.

I usually don't use HAL for the important stuff, but until now FDCAN was only a feasability check.

And yes, it works, although I had some problems getting the 8 Mbps running...

static uint32_t HAL_RCC_FDCAN_CLK_ENABLED = 0;
 
void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* phCan)
{
	GPIO_InitTypeDef GPIO_InitStruct = { 0 };
 
	if( phCan->Instance == FDCAN1 )
	{
		/* FDCAN1 clock enable */
		HAL_RCC_FDCAN_CLK_ENABLED++;
		if( HAL_RCC_FDCAN_CLK_ENABLED == 1 )
		{
			__HAL_RCC_FDCAN_CLK_ENABLE();
		}
 
		__HAL_RCC_GPIOH_CLK_ENABLE();
		/** FDCAN1 GPIO Configuration
			PH14	------> FDCAN1_RX
			PH13	------> FDCAN1_TX
		*/
		GPIO_InitStruct.Pin 	= FDCAN1_RX_Pin | FDCAN1_TX_Pin;
		GPIO_InitStruct.Mode 	= GPIO_MODE_AF_PP;
		GPIO_InitStruct.Pull 	= GPIO_NOPULL;
		GPIO_InitStruct.Speed 	= GPIO_SPEED_FREQ_LOW;
		GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
		HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
 
	/* FDCAN1 interrupt Init */
		HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 10, 0);
		HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
		HAL_NVIC_SetPriority(FDCAN1_IT1_IRQn, 10, 0);
		HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
 
		/* interrupt enable, all lines to 0 */
		phCan->Instance->ILS = 0;
		phCan->Instance->IE = (FDCAN_IE_DRXE | FDCAN_IE_RF1NE | FDCAN_IE_RF0NE );
		phCan->Instance->ILE = FDCAN_ILE_EINT0;
		phCan->Instance->IR = 0xFFFFFFFF;
	}
 
}

And in the IRQ handler I check its source, set some flags which I check later in main, then call the HAL IRQ handler to reset register flags.

/**
 * @brief This function handles FDCAN1 interrupt 0.
 */
void FDCAN1_IT0_IRQHandler(void)
{
	/* get PTP time */
	ETH_PTPTime_GetTime(&sTimeCanRx);
 
	if( FDCAN1->IR & FDCAN_IR_RF0N )
	{
		sCan1RxFifo0.RxdIrq = 1;
		sCan1RxFifo0.sTimeRx.seconds = sTimeCanRx.seconds;
		sCan1RxFifo0.sTimeRx.nanosec = sTimeCanRx.nanosec;
	}
	if( FDCAN1->IR & FDCAN_IR_RF1N )
	{
		sCan1RxFifo1.RxdIrq = 1;
		sCan1RxFifo1.sTimeRx.seconds = sTimeCanRx.seconds;
		sCan1RxFifo1.sTimeRx.nanosec = sTimeCanRx.nanosec;
	}
	if( FDCAN1->IR & FDCAN_IR_DRX )
	{
		sCan1RxBuffer.RxdIrq = 1;
		sCan1RxBuffer.sTimeRx.seconds = sTimeCanRx.seconds;
		sCan1RxBuffer.sTimeRx.nanosec = sTimeCanRx.nanosec;
	}
 
	HAL_FDCAN_IRQHandler(&hCan1);
}

Hello,

the issue is resolved:

Issue visible in the Code:

hfdcan2.Init.StdFiltersNbr = 0;

Solution, change the Config in the Stm32CubeIde, set the number of filters to 1, the generated code will be:

hfdcan2.Init.StdFiltersNbr = 1;

Thanks a lot to everybody supporting the case.

Best Regards, Seppel

P.S. It is so obvious that if you use a filter the number of filters should not be zero. But as always: "You know afterwards, what you could have known in advance". 8)