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QSPI fail on memory mapped read after DMA page programm

DDU
Associate II

Hi

We are facing a problem while trying to read data out of QSPI flash in memory mapped mode shortly after programming a page in DMA mode. We see that the read data is corrupted / unexpected altough flash hast he correct data.

Our steps to reproduce the issue :

  • Update a data in one sector
    • Erasing a sector (4 KBYtes) by
      • Entering write mode (HAL_QSPI_Command/QSPI_CMD_WRITE_ENABLE (0x06))
      • Send erase command (HAL_QSPI_Command/QSPI_BlockErase_4k (0x20))
      • Wait for reading status register (HAL_QSPI_Command/QSPI_CMD_READ_STATUS_REG1 (0x05), HAL_QSPI_Receive) doesn’t have QSPI_REGISTER_WIP set (bit 0).
    • Writing just a single page (256Bytes)
      • HAL_QSPI_Command_IT /QSPI_CMD_PAGE_PROGRAM (0x02)
      • HAL_QSPI_Transmit_DMA (data)
      • On transfer complete a callback is triggered from the interrupt
  • Enable memory mapped mode and read the data
    • Apply Errata suggestions (STM32L471xx Errata sheet , 2.6.5 Wrong data can be read in memory-mapped after an indirect mode operation)
    • Enter memory mapped mode HAL_QSPI_MemoryMapped/QSPI_CMD_FAST_READ (0x0B)
    • Copy data from a memory mapped region. The red buffer contains unexpected values.

Observations :

  • QUADSPI_CCR FMODE indicates indirect write mode before entering memory mapped mode (so according to errata suggestions we are resetting QUADSPI_AR to 0.
  • If we add significant delay before going to memory mapped mode (~2000 NOPs), then the red data is correct
  • If we don’t use DMA to write, it’s also OK
  • In case of failure we see that we receive transfer complete indication before we try to switch to memory mapped mode (also protected by a mutex)

Do you have any suggestions how we can proceed and what we could check next to resolve this problem?

THX, Daniel

PS:

CPU: STM32L4A6VG

STM32L4xx HAL version: 1.8.3 (from STM32Cube_FW_L4_V1.12.0)

1 REPLY 1

Do you check WIP after write?

Not using DMA for writing here, you might need to review signalling with logic analyser. If there is a signalling issue work with an ST FAE to resolve.​

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