Questions on memory map of STM32F439

[kartik]

Posted on June 26, 2014 at 02:24

I've spent about three months working on the STM32F439 Evaluation platform and this is my first time taking on an embedded platform single handed and developing software on it, so please forgive my ignorance. 

I'm trying understand my applications use of SRAM to get an idea of how much memory I'm actually using. I'm using IAR for my tool chain. So according to the STM32F4xx reference manual and the comments in the stm32f43x9 bsp provided in the demo application supplied, SRAM1 is 112 KB, SRAM2 is 16k and SRAM3 is 64KB and is visible only to the processor totalling to 192KB. However, the data sheet for the STM32F439NI chips say that there is 256KB of SRAM available. Where is the extra SRAM or am I missing something?Here is the peripheral map I got from stm32439xx.h&sharpdefine FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region                         */&sharpdefine CCMDATARAM_BASE       ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */&sharpdefine SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region                             */&sharpdefine SRAM2_BASE            ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region                              */&sharpdefine SRAM3_BASE            ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region                              */&sharpdefine PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */&sharpdefine BKPSRAM_BASE          ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region                         */&sharpdefine FMC_R_BASE            ((uint32_t)0xA0000000) /*!< FMC registers base address                                                 */&sharpdefine CCMDATARAM_BB_BASE    ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region  */&sharpdefine SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region                             */&sharpdefine SRAM2_BB_BASE         ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region                              */&sharpdefine SRAM3_BB_BASE         ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region                              */&sharpdefine PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                                */&sharpdefine BKPSRAM_BB_BASE       ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */Also, STemWin uses a region of memory as its video bufferes where it has two layer buffers worth of memory. I'm not sure where this actually maps to. The addresses according to the LCDconf.c file supplied in the BSP package supplied with evaluation board are:

&sharpdefine

LCD_LAYER0_FRAME_BUFFER ((

int

)

0xC0200000

)

&sharpdefine

LCD_LAYER1_FRAME_BUFFER ((

int

)

0xC0400000

)Can someone clue me in on this.Finally, I'm trying to understand how much memory is actually being used when I build my code and I was wondering if someone can help me understand the output from the IAR compiler.I configure the build window to output all MEssages which includes the code size. At the end of the build I get this:  110 576 bytes of readonly  code memory   373 351 bytes of readonly  data memory   177 897 bytes of readwrite data memory Do the readonly code and data memory always reside in flash or are they transferred to SRAM during the bootup process ? Also based on the read write memory usage, should I interpret that my SRAM usage is 173 Kb, Implying that I'm using 173 / 192 KB ?Any help here would be much appreciated.RegardsKartik #stm32f439

[Tesla DeLorean]

Posted on June 26, 2014 at 03:17

64 + 112 + 16 + 64 = 256

The CCM is 64KB of RAM at 0x10000000 and is for the use by the CPU, not DMA The linear region of 192KB is situated at 0x20000000

[raptorhal2]

Posted on June 26, 2014 at 03:21

You are missing counting the 64 KB of core coupled memory (CCM) in Block 0.

See the Memory Map figure in the data sheet. Cheers, Hal

[kartik]

Posted on June 26, 2014 at 18:38Thanks a lot guys. That explains a lot. Any ideas about where the video buffers are in the STemWin config code ? ThanksKartik

[Tesla DeLorean]

Posted on June 26, 2014 at 19:44

0xC0000000 is the SDRAM in the external memory space (STM324x9I-EVAL), the SDRAM is in a different bank on the STM32F429-DISCO at 0xD0000000

The external memory would need to be initialized before the C run-time start up code would be able to access it.

[kartik]

Posted on June 27, 2014 at 00:17Aah this makes sense. I did copy some BSP code that initialized SDRAM on the evaluation board and can see it being called. Thanks a lot Clive1, appreciate the help. Can you point to any literature that tells me that the SDRAM address is set to 0xC0.... I was under the impression that acessing external SDRAM would have to use driver read write calls to access the addresses and that we couldn't just dereference an SDRAM memory address. IS that what the DMA2D is doing, SDRAM to LTDC buffer transfer ? In the LCDConf Driver supplied, offsets of these SDRAM addresses are fed directly to the LTDC driver via HAL_LTDC_SetAddress. It appears as though the SDRAM addresses can be directly accessed by the LTDC. Am I right about this? I was under the impression that the LTDC would only be able to read from SRAM. Thanks Kartik

[Tesla DeLorean]

Posted on June 27, 2014 at 01:41

The Data Sheet and Reference Manual, it's connected to FMC 5 or 6 depending on the board design