In fact I have several questions about reception handling of bxCAN and one of them is demonstrated in the title. I will show my questions by an example. ( All the following discussion is based on Section 32.7.3 in STM32F405/415, STM32F407/417, STM32F427/437 and STM32F429/439 advanced Arm<Sup>®</Sup>-based 32-bit MCUs - Reference manual ).
The development tools I have are limited, preventing me from conducting experiments to verify these issues by myself. It will be helpful if ST's technical staff can assist in answering my questions, as these details are not included in the reference manual.
Suppose 4 CAN data frames arrived and they were all stored into FIFO1. Then CPU wrote 1 to RFOM1 for 4 times. This procedure is showed in figure1.
figure 1
We focus on 7 specific moments t0, t1, t2, t3, t4, t5， t6.
We assume that in t0 the FIFO1 is empty, i.e, FMP1[1:0] in CAN_RF1R is 00b. And FIFO lock function is disabled.
I hope someone could confirm whether the following statements are true.
1.The mailbox and 3-level FIFO(Only FIFO1 is used and FIFO0 is excluded in our discussion.) can store up to four different data frames.
2.At t1, FMP1[1:0] in CAN_RF1R is 11b. FULL1 is 1.
The message distribution should seem like figure2.
figure 2
3. At t2, FMP1[1:0] in CAN_RF1R is 11b. FULL1 is 1.
The message distribution should seem like figure3.
figure 3
4.After t3, FMP1[1:0] in CAN_RF1R is 11b. FULL1 is 1.
The message distribution should seem like figure4.
figure 4
5.After t4, FMP1[1:0] in CAN_RF1R is 10b. FULL1 is 0.
The message distribution should seem like figure5.
figure 5
6.After t5, FMP1[1:0] in CAN_RF1R is 01b. FULL1 is 0.
The message distribution should seem like figure6.
figure 6
7.After t6, FMP1[1:0] in CAN_RF1R is 00b. FULL1 is 0.
The message distribution should seem like figure7.
figure 7
8.Atomicity/ Data Consistency of output mailbox is guaranteed. Though the RX FIFO may be over written by new data frames(if FIFO lock is disabled).
9.Final question. The description of RFOM1 in rm0090 reads:
If at least two messages are pending in the FIFO, the software has to release the output mailbox to access the next message.
Cleared by hardware when the output mailbox has been released.
It seems to me that after writing 1 to RFOM1 output mailbox will be released by hardware, and the pending data in FIFO is being copied into output mailbox while RFOM1 remains 1. here comes my question:
--- Is the data consistency guaranteed when RFOM1 remains 1? (I believe there must be a period during which it isn’t since memory WR can’t be done instantly)?
---Should I read back RFOM1 and wait until it becomes 0 before reading the next message in output mailbox?
1 ACCEPTED SOLUTION
Accepted Solutions
