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The linker file is expected to be in the root directory instead of the subdirectoryI have a project that has to compile for two STM32 hardware platforms:- the Nucleo-F446RE development board- the STM32G051 microcontrollerThe project is developed in VS Code.The .ioc file has been moved from the root directory to two subdirectories:./target/nucleo_f446re./target/g051In the file CMakePresets.json        {            "name": "nucleo_f446re",            "inherits": "default",            "cacheVariables": {                "CMAKE_BUILD_TYPE": "Debug",                "STM32_TARGET": "nucleo_f446re"            },            "toolchainFile": "${sourceDir}/targets/nucleo_f446re/cmake/gcc-arm-none-eabi.cmake"        }, The gcc-arm-none-eabi.cmake file is generated by STM32CubeMX. It contains the following line:set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -T \"${CMAKE_SOURCE_DIR}/STM32F446XX_FLASH.ld\"")This means that the linker script is expected to be in the root directory of the projec

Hi all,When I create a TouchGFX application starting from CubeMX, the following folder and its subfolders are not generated:{ProjectName}\Appli\Middlewares\ST\touchgfx_componentsGPU2D is enabled, and “Use GPU2D acceleration” is set to True under the X-CUBE-TOUCHGFX package settings.However, when I create a TouchGFX project using TouchGFX Designer and select the STM32N6570-DK, these folders are generated correctly.Am I missing a configuration step in CubeMX?Thanks so much!

According to the STM32MP257 datasheet:"1× USB 2.0/3.0 high-speed/SuperSpeed dual role data with embedded 480 Mbits/s and 5 Gbits/s PHY" "1× PCI Express with embedded 5 Gbits/s PHY (PHY shared with USB 3.0 SuperSpeed)"I would like to clarify:Can the USB3DR peripheral be used as a USB 3.0 SuperSpeed port while simultaneously supporting USB 2.0 High-Speed operation on the same connector? Is the embedded USB 2.0 PHY always available when the USB3DR interface is enabled? When PCIe is not used, can the USB3DR interface provide both the 480 Mbit/s USB 2.0 and 5 Gbit/s USB 3.0 links together as a standard USB 3.x port? Is the PHY sharing limitation only between PCIe and USB 3.0 SuperSpeed, or does it also affect USB 2.0 functionality?Any clarification on the USB/PCIe PHY sharing architecture would be appreciated.

Hello, I’m trying to initially build the Distribution-Package 6.2.0 (v26.02.18) as stated in the Wiki (https://wiki.st.com/stm32mpu/wiki/STM32MPU_Distribution_Package#Initializing_the_OpenEmbedded_build_environment)I am using a VM in Virtual Box running Ubuntu 24.04.5 LTS.I attached the log file.Any help is appreciated :)Thanks in advance.Ben

Not able to log imu(ASM330LHH) data in the sdcard tried multiple times not detecting correct imu data is null only 

Hello, I am currently trying to set up the STM32H745ZIT6, and the datasheet wasn’t too clear about how to wire up the 3 VCAP pins. It stated to use 2x 2.2uF caps, but doesn’t state which pins. I found an old forum with many different configurations, typing all VCAP pins together, no VCAP pins tied togehter, and only two VCAP pins tied together. I just wanted some clarification on how I should be typing these pins.

 For diode part number ESDLIN1524BJ following information is needed:1) Housing/Encapsulation material (Example HENKEL GR-646)2) CTE (Co-efficient of thermal expansion) for Housing/Encapsulation material3) Lead Frame Material (Example Alloy42)4) CTE (Co-efficient of thermal expansion) for Lead Frame Material

Hi all, hoping some of the veterans here or an ST engineer can help. Long debug session, board-level causes systematically ruled out, looking for input on what's left.Setup: SPC58NH92E7RMI0X (eLQFP176), custom board, internal-regulator-with-external-ballast configuration (BC868ballast transistor).Core symptom: VDD_HV_IO_MAIN, fed from a confirmed-clean 3.3V LDO, never reaches 3.3V once connected to the MCU — plateaus around 1.3–1.8V regardless of available current (tested to 800mA–1A limit, current settles 500mA–1.5A depending on config). VDD_LV never stabilizes at 1.2V as a direct consequence. MCU runs very hot; the ballast transistor does not.Ruled out:Wrong part (physically confirmed) Wrong pinout: every power/config/Ethernet pin checked against the official IO definition workbook Passive short on VDD_HV_IO_MAIN (~2.9kΩ unpowered, not a short, higher than an unrelated rail on the same board measured the same way) Wrong component values/orientation on the ballast circuit A real power

I am currently evaluating the following ST platform for an IO-Link Device application: MCU Board: NUCLEO-G071RB IO-Link Expansion Board: X-NUCLEO-IOD02A1 IO-Link Transceiver: L6364Q Software Package: X-CUBE-IOD02 Development Environment: STM32CubeIDE The STM32G071RB example project included in X-CUBE-IOD02 builds and runs successfully.However, based on the documentation and the provided ministack library, the current software package appears to be based on IO-Link Interface and System Specification V1.1.2.For a new product development, I would like to use a newer or the latest available IO-Link Device Stack.I would appreciate any information on the following: Is there a newer version of X-CUBE-IOD02 that supports an IO-Link specification later than V1.1.2? Is there an updated version of the following ministack library that supports a newer or latest IO-Link specification? iol_device_ministack_stm32g0_wc32_ot.a If an updated library is available, where can the corresponding li

I am facing an intermittent issue with the STM32N6570-DK when using it with macOS.Setup Board: STM32N6570-DK Host: MacBook Pro STM32CubeProgrammer: v2.23.0 Connection: USB-C hub with USB-A ports ( I am currently using the following USB hub: https://amzn.in/d/02O7R7zS) One USB-A port is connected to the STM32N6570-DK USB1 USB-C port Another USB-A port is connected to the STM32N6570-DK ST-LINK USB-C port Application: AI inference application using the onboard display and USB communication to stream data back to the host Initially, JP2 was configured on pins 1–2 (5V_STLK). IssueWhen using a direct USB-C-to-USB-C connection on Windows, I do not encounter this issue.However, on macOS, a direct USB-C-to-USB-C connection results in DEV_USB_COMM_ERR. Based on a suggestion from a related ST Community discussion (ST-LINK stuck in DEV_USB_COMM_ERR until USB replug after connecting with no target | Community),Also, we found out that a known issue/ limitation regarding this (USB

 I’ve been discovering the different views available in STM32Cube IDE and among them is the Build Analyzer view.In this view I found a section in the RAM called ._user_heap_stack.I searched for it in the linker script and found that it corresponds to the following section : /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */._user_heap_stack :{. = ALIGN(8);PROVIDE ( end = . );PROVIDE ( _end = . );. = . + _Min_Heap_Size;. = . + _Min_Stack_Size;. = ALIGN(8);} >RAMWith _Min_Heap_Size = 0x200; /* required amount of heap */_Min_Stack_Size = 0x400; /* required amount of stack */In Figure 1, one can see that the start address of the ._user_heap_stack is 0x2000 002C. This means that the last address of the stack should be 0x2000 002C + 200 + 400 = 0x2000 062C, with the 8 byte alignment that would make it 0x2000 0630. Figure 1 : Screenshot of the Build Analyzer ViewTo make sure my calculations are correct, I added a variable in the linker script (high

The user authentication service is under maintenance on September 17 at 6:00 a.m. CET for approximately 30 minutes. During this period, disruptions can occur. The impact is limited to versions earlier than STM32CubeMX V6.16.0 and STM32CubeIDE V2.0.0. The service returns to normal soon after maintenance is complete.What to do if a problem occursIf issues occur during the maintenance window, use st.com or try again after 30 minutes. If the problem persists after that time, contact ST through the Community for further assistance. Update September 17, 2026:The maintenance was successfully completed as scheduled on September 17.If you encounter any issues, please do not hesitate to contact us.

The user authentication service is under maintenance on September 17 at 6:00 a.m. CET for approximately 30 minutes. During this period, disruptions can occur. The impact is limited to versions earlier than STM32CubeMX V6.16.0 and STM32CubeIDE V2.0.0. The service returns to normal soon after maintenance is complete.What to do if a problem occursIf issues occur during the maintenance window, use st.com or try again after 30 minutes. If the problem persists after that time, contact ST through the Community for further assistance. Update September 17, 2026:The maintenance was successfully completed as scheduled on September 17.If you encounter any issues, please do not hesitate to contact us.

I’m looking for a couple of Op Amps for a project, they really need to have a long production lifetime.The TSV781 is one I’m looking at based on the specs., but I’m confused about how the 10 year commitment works for these (it is obviously different to the STM32).The product page has the Ten Year stamp, which to me implies 10 years from now (or at least this year), however the date shown is  November 2029 (which agrees with the longevity page) - only 3 years!The further problem is that the device data sheet says initial release July 2022 which would mean only 9 years support.Obviously I need to use a different device, but how to choose?My apologies if this is in the wrong place, but “Analog and Audio” does not appear in the forum list.

Hi,Is there any stabilization or warm-up time needed by STM8S controller when interfaced with ADC for calibration?Usually for ADCs there is a warm-up time, so wanted to know if this MCU also has a warm-up time.

1.I would like to connect 6 Industrial Sensor which support (4-20ma) or (0-10 Volt ) to STM32H723ZGT6.Guide me both Manual circuit or any IC which can perform below TVS / series protectionPrecision shunt / scalingRC anti-alias filter2.How i can connect and what need to be done for io protection from Reverse polarity and Surge protection 

Hello, I was wondering where can I find the Pick n place file to create the dev board. on the official site there is the BOM and the gerber files, but without the pick N place I can’t actually assemble it.Thanks for the helpRoman

Hi,I am using STM32G431CBU6 with HSI16 as the only clock source (no external crystal on the board), and I need to budget the resulting frequency error. I have a few questions about DS12589 Rev 2 (October 2019), Table 44 "HSI16 oscillator characteristics", page 107, and Figure 23 on the same page.Q1 (main question) — Are fHSI16 and Δtemp(HSI16) additive, or is Δtemp inclusive?Table 44 lists two separate parameters:Symbol Conditions Min Max fHSI16 VDD = 3.0 V, TA = 30 °C 15.88 MHz 16.08 MHz Δtemp(HSI16) TA = 0 to 85 °C −1 % +1 % For a single device over the 0 to 85 °C range, is the worst-case total frequency error:(a) −7500 ppm − 10000 ppm = −17500 ppm … +5000 ppm + 10000 ppm = +15000 ppm (i.e. the two parameters add), or (b) ±10000 ppm (i.e. Δtemp already includes the initial tolerance at 30 °C)?This makes a large practical difference for bit-timing budgets, so I would like to be sure.Q2 — Is a typical temperature coefficient (ppm/°C) available?Figure 23 shows mean/

Hello ST Community,I am following the tutorial "How to deploy an AI model on STM32N6 – Neural-ART":https://dev.st.com/edge-ai-docs/general/latest/en/docs/tutorials/how-to-deploy-ai-model-stm32n6-neural-art.htmlI successfully completed all the steps, but when building the application in STM32CubeIDE, I get the following linker error: arm-none-eabi-gcc -o "Test_inference_model_Appli.elf" @"objects.list" -l:NetworkRuntime1201_CM55_GCC.a -mcpu=cortex-m55 -T"C:\Users\ROMAINC\Test_inference_model\STM32CubeIDE\Appli\STM32N657X0HXQ_ROMxspi2.ld" --specs=nosys.specs -Wl,-Map="Test_inference_model_Appli.map" -Wl,--gc-sections -static -Wl,--cmse-implib -Wl,--out-implib=./secure_nsclib.o -L../Middlewares/ST/AI/Lib --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-groupC:/ST/STM32CubeIDE_2.1.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../..

Hello,I am using an STM32N657 on a custom board.I need to use PA6 as PIXCLK, so I would like to move the BOOT1 function from the default PA6 pin to PN10.According to the STM32N6 BootROM/OTP description, I understood that BOOT1 can be remapped using OTP19 (BOOTROM_CONFIG_10): I programmed OTP19 with 0x15200000 in STM32CubeProgrammer to change BOOT1 from PA6 to PN10.Before programming OTP19, I could connect to the MCU normally through ST-LINK/SWD using PA6 as BOOT1.However, after programming OTP19 to 0x15200000, I can no longer connect to the MCU.The same issue has occurred on more than one custom board.My test conditions are:MCU: STM32N657 I/O supply voltage: 1.8 V BOOT1 remapped to: PN10 OTP19 programmed value: 0x15200000 PN10 is held HIGH before and during reset ST-LINK detects the target voltage During connection, STM32CubeProgrammer can sometimes identify Device ID 0x486, but then reports that the connection to device 0x486 is lost The board works and SWD connection is available bef

Hello guys. I’m currently trying to implement a CI/CD pipeline on my project, using a dedicated RPi device (Raspbian) as a test-bed. I use a python script to generate the cmake.txt file and then the arm libraries and ninja to build the .bin file and the programmer cli to flash it onto my device. The thing is that my approach works for now, but trying to include external packages like CMSIS dsp, or user provided libraries is such a huge pain. It works for now that the package is a very specific one, but this might change in the future, with the inclusion of new packs/libraries.So my question is, what is the best way -- Generate the cmakelist file that also includes the external packs/librarie. Is there a possibility to use an extension on Vs code server installed on my RPi ? -- Link said packages/libraries. I currently have a copy of a specific version of the Board FW files where most of the middleware files are, my imported libraries and the external CMSIS packs. Any advice would be we

Greetings,I am not quite a USB, or USBX, expert, but I do have a question.I have a custom HW design utilizing the H573, and the USB FS port, which according to the datasheetsupports a max of 8 configurable endpoints.We have a USB Hub chip integrated into the HW design, and hoped to support 4 USB devices behindthe hub. Assuming that each device is a 2.0 USB Flash Drive (Sandisk, or whatever vendor),and each USB Flash drive consumes 3 endpoints (control, IN and OUT), this is twelve endpoints just forthe flash drives.The number 8 (endpoints), is fixed in STM32H5 hardware? Am I correct in saying that the four flash drive application will never work? ThanksKen

Hello,I have recently tested the timing of DMA reading data from GPIO on an STM32H755 and found that the required input signal hold time is shorter than what is described in AN4031. I would like to ask whether my understanding is incorrect or if it is due to architectural differences in the chip.Test platform and configuration:Hardware: NUCLEO-H755ZI-Q, using the CM4 core, CM7 idle.System clock: SYSCLK = HCLK = PCLK2 = 8 MHz, APB2 timer clock = 8 MHz.Timer: TIM1 configured in PWM mode, CH1 outputs a 1 MHz square wave with 50% duty cycle, and the DMA request for the CC1 event is enabled.DMA: Using DMA1_Stream0, peripheral address is GPIOA->IDR, data width half-word (16 bits), peripheral address not incremented; memory address points to an SRAM array, half-word width, address incremented. FIFO disabled.External signal: A signal generator produces a 1 MHz PWM signal connected to PA0, and the phase is adjusted so that its edges align with the edges of the TIM1_CH1 output.Test method:Sta

Dear STM Community Team,We are working with the STM32N657X0H3Q microcontroller in our custom hardware design. We have interfaced S80KS5123GABHB020 Octal RAM devices with the controller using the XSPI interface.In our design, we are using a dual Octal memory configuration as described in the STM32N6 Reference Manual. The two 8-bit memories are configured to operate together as a 16-bit external memory interface.We would like your guidance regarding the correct STM32CubeMX configuration settings for this dual Octal memory setup.Our configuration details are: MCU: STM32N657X0H3Q External Memory: S80KS5123GABHB020 Interface: XSPI Memory Configuration: Dual Octal mode (two 8-bit memories forming a 16-bit interface) Intended usage: External RAM for (ltdc)framebuffer Memory mapped access: XSPI memory-mapped mode Could you please confirm the recommended STM32CubeMX settings for the following parameters? XSPI mode selection: Should the configuration be set as HEXASPI mode? Are

Hi, In the STULPI01BTBR datasheet I could find the timing spec only for SDR mode. I need to verify the DDR mode on our board and could not find the DDR mode timing spec. Can anyone please help to find the timing spec for ULPI interface DDR Mode. Regards,Shivakumar