ISM6HG256X / Shock event

[David45]

Hi, 

 

we use on a design a ISM6HG256X. We want to detect a shock end event using the interrupt INT2.

We use this configuration :

    * INT2_HG_WU = 0

    * INT1_HG_WU = 0

    * INT2_HG_SHOCK_CHANGE = 1 

    * INT1_HG_SHOCK_CHANGE = 0

Logically, we should have an interrupt INT2 only when the shock event end is detected. In fact, we have an interrupt at wake_up event and at the shock end and sometimes we have interrupt on INT1. 

We use a STEVAL - MKI248KA to evaluate the ISM6.

Do you have some tips to solve this problem?

[Federica Bossi]

Hi ​@David45 ,

On ISM6HG256X, the high-g wake-up and shock interrupts are ORed, so a shock event is not reported as a “pure” end-of-shock signal only. To identify the exact phase, read ALL_INT_SRC first and then HG_WAKE_UP_SRC, and check HG_SHOCK_STATE / HG_SHOCK_CHANGE_IA to distinguish wake-up, shock entry, and shock end.
Also make sure no other sources are routed to INT1/INT2, because multiple interrupt sources are combined with an OR logic on the same pin.
Finally, when the high-g function is enabled, the low-g accelerometer must be in high-performance or high-accuracy ODR mode; low-power, normal, and ODR-triggered modes are not compatible.

[David45]

Hi Frederica, 

 

Thanks for your answer. We will check the INT sources in case where we forget one sources. 

Just a question about low g, we need to be in high performance in our case but the low g could stay in power down or it must run all the time we use the High g ?

 

 

 

 

[Federica Bossi]

Hi ​@David45 ,

When the high-g accelerometer is enabled, the low-g accelerometer cannot stay in power-down. It must run in High-Performance or High-Accuracy ODR mode. However, the low-g and high-g ODRs are independent and can be configured separately.