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Post edited by a ST moderator to be inline with the community rules especially on the code sharing. In next time please use </> button to paste your code. Hi I am struggling getting context save restore working correctly, when operating the HASH hardware block using polling mode.Basicly the flow is like this: /* --- STEP 1: Start hashing first chunk --- */ HAL_HASHEx_SHA256_Start(&hhash, input1,strlen((char*)input1), digest,HAL_MAX_DELAY); /* --- STEP 2: Save context --- */ HAL_HASH_ContextSaving(&hhash, context); /* --- STEP 3: Restore context --- */ HAL_HASH_ContextRestoring(&hhash, context); /* --- STEP 4: Continue hashing --- */ HAL_HASHEx_SHA256_Accumulate(&hhash, input2, strlen((char*)input2)); /* --- STEP 5: Finalize hash --- */ status = HAL_HASHEx_SHA256_Finish(&hhash, digest, HAL_MAX_DELAY); However when calling HAL_HASH_ContextSaving the DINIS is not equal to 1 and CSRx registers return zeros as stated in the reference manualHow do it

I got an error when downloading the .sfi file to STM32H753II using the STM32Programmer_CLI, my HSM version is V2AE.The error message is as follows:What its mean?V2AE cannot support STM32H753,and must use HSM_V1?or H753 cannot support SFI ?I’m a new use about SFI.Looking forward to your reply.

Hi,I am using SBSFU v2.8 with an STM32H750. I have successfully booted my firmware without any protections. I have also enabled protections and succeeded all tests in the test suite provided in the example code in sfu_test.c.However, when I attempt to boot my firmware with any protections enabled at all, I get the following, followed by a reset.This is happening at the first control flow check at line 1092 in sfu_boot.c.In my research, I found this post. I replicated it and included app_sfu.h in sfu_boot.h. It works now.I would like some clarification on this whole situation. Is this a bug? or is my build system just not including app_sfu.h appropriately ?Thanks!

Hello, I am working with an STM32 B-U585I development kit. The board has been previously used, and some protection-related configurations have been modified. I am now trying to perform new tests on the device, but I believe I am unable to bypass the current protection settings. I would appreciate your assistance on this matter. A TFM application was previously installed on the board. When connecting via STM32CubeProgrammer, I observe the following: 1. Connection settings: I connect with the following configuration: Boot0 = 1 Port: SWD Mode: HotPlug Reset Mode: Hardware 2. STLinkUpgrade tool: When opened, the ST-LINK is identified as: Type: STM32Debug+VCP 3. STM32CubeProgrammer observations: RDP = 0xDC (Level 1, read protection of memories) TrustZone = 1 OEM1LOCK = 1 OEM2LOCK = 0 I do have the required password to unlock RDP, and I am able to successfully unlock the RDP protection. My development environment: STM32CubeIDE v1.19.0 To verify firmware download capability, I created

I have STEVAL-PTOOL4A connected to drive - 12V sensored BLDC motor - 2 pair poles - 16k rpm I faced 2 problems - First motor doesn't operate with potentiometer when used alone without the workbench- leds doesn't  light(( THE SYSTEM POWERED BY 12VDC 10A))

Hello,We are using the STM32N6 series MCU in our project and encountering issues during debugging. I’ve attached a screenshot of the error message we are seeing.We followed the steps outlined in this guide:https://community.st.com/t5/stm32-mcus/how-to-debug-stm32n6-using-stm32cubeide/ta-p/800547However, the code cannot be debugged from external flash (in dev boot mode).But, when we boot from flash (flash boot) and the debugger is not connected, the code runs as expected.Also, debugging from RAM with FSB works, but debugging the App code from RAM fails and gives the same error.Based on the information in this page:https://wiki.stmicroelectronics.cn/stm32mcu/wiki/Category:Security_with_STM32N6,could this issue be related to the STM32N6's debug security features?Best regards,Egemen Aksoy

It would be nice if the further versions could be running on case sensitive file system on macOS.Currently I need to use an USB key formatted APFS only. Then i can run the installer and install the programmer on this USB stick. As I most of the time only need the command line tools (*CLI) I copied the binaries and some folders with data on my case sensitive disk. They work fine. Only the GUI is not possible on the case-sensitive file system. 

Split from The MCU selector cannot be opened, but the board selector can be opened normally.That issue is confirmed as solved; so this is a different issueI had exactly the same issue and could be solved by removing xcubeai.But it's confusing while reading this thread, another reply was marked as solution. Actually deleting .stm32cubemx/finder doesn't work.  

Hello STM32 Community,I am currently developing a USB Type-C Active Cable application using an STM32 with the official USB-PD Middleware.My Goal: The MCU needs to behave as an EMarker/Active Cable. Therefore, it should:Ignore all SOP messages on the CC line (no response and no GoodCRC ).Only respond to SOP' and SOP'' messages.Able to monitor (Snoop) SOP messages exchanged between the Source and Sink to maintain state awareness.The Problem: In the current X-CUBE-USB-PD middleware and STM32CubeMX configuration, there is no explicit option to disable SOP handling while keeping SOP'/SOP'' active. Since GoodCRC is typically handled by the UCPD hardware autonomous logic to meet the strict tTransmitSOP timeout, the hardware automatically sends a GoodCRC when it detects a valid SOP message CRC, even if the firmware isn't intended to process it.Technical Details & Questions: I am looking for a way to bypass or disable the hardware-level auto-response for SOP only.Register Control: Is there

I have a STM32WB05TZF6TR. All VCCs are running off 1.8V. I'm trying to use PA8 and PB5 with 3.3V 10k pullups. But the signals are being clamped at 2.5V. I had expected this not to happen, as they are supposed to be 5V tolerant. Does anyone know what's happening here? There's nothing connected to the pins besides the pullups. I have a bare STM32CubeMX project, with just this GPIO init:void MX_GPIO_Init(void){ GPIO_InitTypeDef GPIO_InitStruct = {0}; /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); /*Configure GPIO pin : PB5 */ GPIO_InitStruct.Pin = GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); /*Configure GPIO pin : PA8 */ GPIO_InitStruct.Pin = GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); } Much appreciated,David 

In ds H5E5 is given:  3x 12b ADCbut on selector is shown:...so secret 3 x 16b ADC there - or error in table ?  

I want to design according to the Figma design, but I have no clue.How can I make the menu follow the selection in the simulator? If I want the last menu to scroll down.

Hello,I am planning to use the TLV320AIC23B audio codec with the STM32H7B3LIH6Q controller.Kindly confirm:Is TLV320AIC23B compatible with STM32H7 (using SAI/I2S for audio and I2C for control)?Any specific requirements for clock (MCLK) or configuration to ensure proper operation?Thanks.

I am using the NUCLEO-WL33CC1 (for 868 MHz freq) and I tried the LPAWUR feature based on the Github examples that you provided:https://github.com/STMicroelectronics/STM32CubeWL3/tree/main/Projects/NUCLEO-WL33CC/Demonstrations/LPAWUR/LPAWUR_WakeupRadio_Rxhttps://github.com/STMicroelectronics/STM32CubeWL3/tree/main/Projects/NUCLEO-WL33CC/Demonstrations/MRSUBG/MRSUBG_WakeupRadio_Tx The issue is that the range that I get is a max of 3 meters, no more that this. I already soldered the C3 capacitor, that is by default missing, with a value of 100pF. The L3 is 5.6nH and L4 is 6.8nH based on the schematics (MB2029) of the NUCLEO witch matches the values that are in the User Manual of the Nucleo (UM3418). Questions:Is there anything that I am missing here in order to get a better range for the LPAWUR feature ?Should I be using a higher power Tx mode to get a better range, on the Github example the Tx power is set to 14 dbm ? If I change these value to 20 dbm and to PA_DRV_TX_TX_H

Hello everyone,   i want to build a CAN FD network with three NUCLEO-C092RC boards. So far i can transmit frames, as i can see on an oscilloscope. But the moment i connect TWO boards, the interrupt is not triggered. My code should activate user LED2 if it receives a frame with one specific id: Board 1 (0x101) triggers LED when receiving message 0x344 or 0x234 Board 2 (0x234) triggers LED when receiving message 0x344 or 0x101 Board 3 (0x344) triggers LED when receiving message 0x101 or 0x234   i use a nom. baudrate of around 500 kbit/s and data baudrate of 1 Mbit/s with a clock of 40 MHz (HSE). The Boards are connected with two short (10cm) twisted jumper cables and the jumpers for the 120 Ohm resistor are also plugged in on both baords. when i test it in external loopback mode, it works (with ident. change) Could this just be a problem with my wires (reflexion , parasi. C ,etc.)?   thanks a lot for the help

Hello, as in the title I'm facing issues with high intensity BLE transfers (~4 writes and 4 reads and indicates per second) on X-NUCLEO-ST67W71 paired with STM32N6570-DK.Randomly during the transfer I'm encountering this error which simply breakes the communication with ST67:ST67 Log: [ERROR] [1055938] [spi_xfer_engine] (spi_iface.c:448) waiting for spi txn ready timeouted ST67 Log: [ERROR] [1057938] [spi_xfer_engine] (spi_iface.c:448) waiting for spi txn ready timeouted ST67 Log: Timeout waiting for tx ST67 Log: [WARN] [1058941] [ST67Task] (st67_app.c:1138) Set read data error! ST67 Log: [ERROR] [1059938] [spi_xfer_engine] (spi_iface.c:448) waiting for spi txn ready timeouted ST67 Log: [ERROR] [1061938] [spi_xfer_engine] (spi_iface.c:448) waiting for spi txn ready timeouted ST67 Log: [ERROR] [1063938] [spi_xfer_engine] (spi_iface.c:448) waiting for spi txn ready timeouted ST67 Log: Timeout waiting for tx ST67 Log: [WARN] [1063951] [ST67Task] (st67_app.c:1143) Data indication error! ST

Hi Team,   I am facing to connect with SR5E1-EVBE7000P board. I give below the issue. Can anyone help me to resolve this issue   Error in final launch sequence:   Failed to execute MI command: -exec-run Error message from debugger back end: Don't know how to run. Try "help target". Failed to execute MI command: -exec-run Error message from debugger back end: Don't know how to run. Try "help target". Don't know how to run. Try "help target".

Hi!I having some issues with Linux at startup. It seems that it disabling the Bucks/LDOs at startup.vddio2: disabling vddio3: disabling vddio4: disabling vddcore: disabling v1v8: disabling v3v3: disablingWhy does this occur?Here is the complete output as attached file. As you can see, I have set up my own outputs for error handling. The device three can be found here:https://github.com/DanielMartensson/Watermelon-Wine-1A/tree/linux-testing/watermelon-wine-os%2Fcubemx%2FCA35%2FDeviceTree%2FfirmwareGood to know:clk_get_index = 143 is USART6.I have activated the RNG for TF-A only. It seems not to wake up. It's the same default configuration as DK. 

In STM32CubeMX, here is the orientation for a chip with a red dot marking pin 1 at the top left when text reads from left to right.In real life, here is the orientation for a chip with a red dot marking pin 1. As far as I'm aware, all STM32 chips are oriented like this, with pin 1 at the bottom left when text reads from left to right. Why is the text rotated 90 degrees differently? Is this intentional? If there is a reasonable explanation, I'm interested in hearing it. It seems to only add confusion. Wouldn't it make more sense if the default orientation (or at least the text orientation) to match between the two? In STM32CubeMX, you can rotate the part for convenience. This is useful. However, the text also rotates, so if you put pin 1 in the bottom left like in reality, the text is now rotated. (This is the same story in STM32CubeMX2.) 

I have a suggestion for the STM32CubeMonitor-Power application.For the ultra low power applications it would be great if the Y-axis could be logarithmically scaled, so that the area around 0.5-100 µA is more detailed (sleep mode) compared to the active mode (1-2 mA). As it is now I cannot quantify the current usage with a glance when the device is sleeping.I would very much like this to be added.Greetings,Rico

Hello,I am using X-CUBE-EEPROM as a mean to store variable in internal FLASH memory on STM32U5G9-DK2 board. Here is my function where a variable in flash:static FLASH_STATUS flash_slot_write_shared_key(const FLASH_INDEX *index, uint8_t slot, uint8_t *shared_key) { if (slot > FLASH_SLOTS_NUMBER) return FLASH_WRONG_PARAM; if (shared_key == NULL) return FLASH_NULL_PARAM; EE_Status ee_status = EE_WRITE_ERROR; HAL_FLASH_Unlock(); taskENTER_CRITICAL(); ee_status = EE_WriteVariable96bits((uint16_t)index->entries[slot].addr, (uint64_t *)(shared_key)); if (ee_status != EE_OK) return FLASH_ERROR; ee_status = EE_WriteVariable96bits((uint16_t)index->entries[slot].addr + 1, (uint64_t *)(shared_key + 12)); if (ee_status != EE_OK) return FLASH_ERROR; ee_status = EE_WriteVariable32bits((uint16_t)index->entries[slot].addr + 2, *(uint32_t *)(shared_key + 24)); if (ee_status != EE_OK) return FLASH__ERROR; ee_status = EE_WriteVariable32bits((uint16_t)index->entries[

The STM32MP135 is powered by PMIC1A. After initial power-up, the voltage at BUCK4 is normal at 3.3V, but during U-Boot flashing, the output voltage at VOUT4 drops to only 2.4V, causing the flashing to fail. The VDD and VDDQ pins of the eMMC are powered by the same power rail, VOUT4.

I am trying to understand one point in the official VL53L8CX datasheet.In the pin description table, pin C5 (MISO) is described for SPI as:“SPI: Main input secondary output. Push-pull output, driven to IOVDD level.”But in Figure 6 (“Typical application schematic for SPI”), the MISO line seems to have a 47 kΩ pull-down resistor to GND.I attached two screenshots:1. the table entry for C5 / MISO2. the SPI typical schematic with the suspected 47 kΩ pull-down highlightedMy question is: how should this be interpretedcorrectly?Does ST mean that MISO is a push-pull output, but an external weak pull-down is still recommended as a default line state? Or is this schematic being misread, and that 47 kΩ resistor actually belongs to another signal?I would appreciate clarification from anyone who has used VL53L8CX in SPI mode or has already resolved this ambiguity.

Hello,I think I have interesting case, but from the beginningI use STM32F446ZEJx and HAL Drivers from STM32Cube_FW_F4_V1.28.3.When I use HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)with Size=5 it internally checks the argumentif ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) return HAL_ERROR;and passes the Size to/* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferSize = Size; hspi->RxXferCount = Size;later it configures the DMA channels,Rx/* Enable the Rx DMA Stream/Channel */ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount)Tx/* Enable the Tx DMA Stream/Channel */ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t

Is there a guide that shows how to set up a CDC USB device on the STM32N6 without using ThreadX in baremetal mode?   I've tried following both, but it seems to hardfault on both examples crash at __lib_init_array(). I've tried increasing the stack and heap sizes to no success:https://community.st.com/t5/stm32-mcus/how-to-use-stmicroelectronics-classic-usb-device-middleware-with/ta-p/599274    https://community.st.com/t5/stm32-mcus/how-to-implement-usbx-in-standalone-mode/ta-p/614435    It's frustrating that the old USB_Device middleware got removed. We shouldn't be forced to use an RTOS where it is not needed...