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Associate
June 16, 2026
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How to Verify ST33KTPM2I Hardware Operation via SPI?

  • June 16, 2026
  • 1 reply
  • 30 views

Hello ST Community,

Before releasing the next revision of our prototype board, we would like to verify that the hardware implementation of the ST33KTPM2I is correct and that there are no hardware design issues.

Currently, the ST33KTPM2I is implemented as an optional component on our board. Before modifying the board design, we would like to perform some basic functional checks to confirm that the device is operating properly.

Our interface is SPI.

Is there any recommended way to verify communication with the ST33KTPM2I? For example, is it possible to read a device ID register or any other status information to confirm that the device is responding correctly?

We reviewed the datasheet, but it does not appear to provide details about accessible registers or a register map. Therefore, we are not sure what commands or procedures can be used to perform a basic hardware validation.

Thank you very much for your support.

Below is our hardware schematic:
 

 

Best answer by Benjamin BARATTE

Hi ​@hahuy,

The layout looks good.

Regarding the TPM register access, you can refer to the TPM PTP specification for the ST33KTPM2I3WBZA9, it’s version 1.06.

Second point, the PTP protocol to access the TPM register requires the SPI CS to be manageable in software as a TPM transaction is made as follow :

  • Lower the CS
  • Write the 4 bytes of registers
  • Read the acknowledge from the TPM until you get 1
  • Read or Write the data of the registers
  • Raise the CS

I know that on some MPU, the CS is managed by the SPI driver and does not support fine grain management of the CS.

Best Regards,

 

Benjamin

 

1 reply

Benjamin BARATTEBest answer
ST Employee
June 16, 2026

Hi ​@hahuy,

The layout looks good.

Regarding the TPM register access, you can refer to the TPM PTP specification for the ST33KTPM2I3WBZA9, it’s version 1.06.

Second point, the PTP protocol to access the TPM register requires the SPI CS to be manageable in software as a TPM transaction is made as follow :

  • Lower the CS
  • Write the 4 bytes of registers
  • Read the acknowledge from the TPM until you get 1
  • Read or Write the data of the registers
  • Raise the CS

I know that on some MPU, the CS is managed by the SPI driver and does not support fine grain management of the CS.

Best Regards,

 

Benjamin

 

hahuyAuthor
Associate
June 17, 2026

Hi Benjamin,

Thank you very much for your detailed explanation and for pointing me to the TPM PTP Specification v1.06.

I will review the specification and verify our SPI implementation, especially the CS handling requirements you mentioned.

If I have any further questions or encounter any issues during testing, I will come back and update this thread.

Thank you again for your support.

Best Regards,
Hahuy