STM32F3: Specifics of using DBG pins for GPIO

[hemogloben]

Posted on January 30, 2017 at 19:07

I'm using a 64-pin STM32F303 in a design and looking into using some of the SW Debug Pins for LEDs.  I've read through the Reference and Programming Manuals and Datasheets for details but am a little confused on some of the specifics and would like some clarification.

How I believe re-assignment of DBG pins as GPIOs works:

• On Reset all JTAG and SW pins are configured as their Alternate Function Debug mode.  The JTAG Debug Port (DP) is active.  Any attempts to change the configuration of the JTAG pins will be ignored (with the exception of SWO which, depending on TRACE setting of DBGMCU->CR, may have it's configuration changed).
• Firmware can disable JTAG and SW by calling...?  I see examples of changing the AFIO->MAPR register on other STM32 processors but can't seem to find an equivalent for the STM32F3.
  • Once JTAG and SW are disabled, attempts to connect with a debugger will fail unless the debugger connected with nRST and resets the MCU.
• If the debugger negotiates a change to SW-DP then all JTAG pins except, now, SWDIO and SWCLK (and potentially SWO), can be re-configured as usual.
  • Is there a way to check what DP is currently selected (so that we can look to see if SW is selected and know that the debugger is connected and not bother trying to re-configure the associated pins)?

Thanks,

Ben

[Uwe Bonnes]

Posted on January 30, 2017 at 19:20

Reg question 2: AFIO->MAPR is for F1, all newer devices have GPIOx_AFRL and GPIOx_AFRH. Look e.g. at rm0316 Chapter 33.4.1 for changing assignment. As Alternate function for debug is 0 and this is the reset value, you only have to change mode

[hemogloben]

Posted on January 30, 2017 at 19:33

Thanks, but I have already seen these.  As per the note in 33.4.4: 

For user software designs, note that:

To release the debug pins, remember that they will be first configured either in input-pull-up (nTRST, TMS, TDI) or pull-down (TCK) or output tristate (TDO) for a certain duration after reset until the instant when the user software releases the pins.

When debug pins (JTAG or SW or TRACE) are mapped, changing the corresponding IO pin configuration in the IOPORT controller has no effect.

So, unless I'm misunderstanding something, if JTAG or SW Debug Port is enabled changing the mode has no effect.

It appears, from documentation, that the JTAG DP is auto-enabled on RESET, and can be changed to SW-DP by the debugger, therefore;

1) How to I detect which Debug Port is currently selected?

2) How to I disable the Debug Ports?

[waclawek.jan]

Posted on January 30, 2017 at 21:59

> So, unless I'm misunderstanding something, if JTAG or SW Debug Port is enabled changing the mode has no effect.

In this context, *enabled* means that the externally connected debugging gadget (e.g. STLink, JLink or similar) has performed an initial sequence on the pins, 'waking up' the on-chip debug facilities.

If you reset the chip without a debugger, you don't need to be bothered by the Debug facilities, simply change the pins mode in GPIO, as Uwe said above.

JW