If you enable Transmission Complete (TC) interrupt flag TCIE in the UART_CR1 register before enabling UART itself, the interrupt will still be be generated.It is not possible to clear TC flag using USART_ICR TCCF in such state. The interrupt handler ...

When SRAM1 is remapped at 0x00000000 address space using SYSCFG_MEMRMP register, SRAM1 cannot be accessed by DMA by its remapped zero-based address. DMA error occurs at the very first transfer and DMA channel becomes disabled.Steps to reproduce:1. Us...

When I write to the DAC register DHR12R2 within less then 1.5 mlsec from enabling DAC, its value is transferred to the DOR2 register as expected, but the voltage on the output pin PA5 remains zero indefinitely. Writing to the DHR12R2 after 1.5 mlsec ...

When reading SRAM2 memory in STM32L496 using ST-Link V2 debug probe, incorrect values are received when read crosses 1k (1024 bytes) boundary. For example, when I try to read 32 bytes starting from 0x100003F0, last 16 bytes that start from 0x10000400...

If we want to pass some information from application running in a thread mode to an interrupt handler using normal SRAM memory (at 0x20000000 address) variables, do we need to do any special synchronization steps (such as calling Data Memory Barrier ...