After some period of approximately 2 years my login is rejected as having incorrect username or password. Careful reentry is not successful, I keep getting the same rejection. I conclude that passwords expire after some time.If that is true, why not ...
Apologies - posted to wrong forum groupHost: amd64, 8GB RAM, 500GB SSD, 440GB available Ubuntu 20.04, all current updatesInstalled the debian amd64 1.11.2 CubeIDE and 6.7.0 MX.Created a simple H750V application using MX. The IDE installed thecurr...
stm32h7xx_ll_utils.c throws a warning "no LL_RCC_CalcPLLClockFreq" function at line 930. The function exists in stm32h7xx_ll_rcc.c but has a conditional compile USE_FULL_LL_Driver.Calls to conditional compiles should be under the same conditional con...
In STLink upgrade download for linux, in the following path: stsw-link007/readme.txttitled STLink firmware upgrade applicationsthe following text paragraph:"On Linux, users must be granted with rights for accessing the ST-Link USB devices. To do...
On the STLINKV3 Mini, what is CN3 used for and what are the signals? Do the two reset pins have a useful user function?No information on this is available in the current user manual.Cheers, Hal
Data rate from ADC 500MHzHow can that be? The maximum F4 ADC clock is 36 MHz. Each conversion takes sampling clocks plus 12 conversion clocks. Ideal data rate is more like 2 MHz, in practice, lower.as I understand it writes a full 16-bits each conver...
What is the reason to have so many shared channels,My guesses:1. For more flexibility in assigning channels to multiple ADCs converting at different frequencies.2. Noise and real estate reduction. Routing to 60 pins would overlap more close proximity...
I'm not an expert on register programming, but if you are not using DMA, you need to reconfigure the ADC channel selection and restart the ADC to convert the second channel after the first conversion.There is only one ADC register to hold the convers...
