Initializing multiple bytes in EEPROM generating RESET in STM8AF5288 MCU

[DMega.1]

I am trying to initialize a section of EEPROM address from 0x40A0 to 0x40B8 in STM8AF5288 MCU. Between I am not able to complete this initialization process & end up getting MCU Reset. Attaching the assembly code that does this action

BSET  _FLASH_CR1,#0

BTJF  _FLASH_IAPSR,#3,unlocked ; check data memory EEPROM write is unlocked

MOV   _FLASH_DUKR,#0xae

MOV   _FLASH_DUKR,#0x56

unlocked:  

    LDW   X,#0x47FF ; p = EEPROM_END                  

    LD    A,(X)         

    CP    A,#0xAA ; when initialization is complete the end of EEPROM address range contains 0xAA

    JRNE  PrepInit     

    JRPL  InitComplete  

PrepInit:

LDW   X,#0x40AD ; load initialization range start address

ContinueInit:

  CLR   A

  LD   (X),A ; clear EEPROM location

  NOP

writing:

BTJF  _FLASH_IAPSR,#2,writing ; check EOP is true to detect EEPROM byte update complete

INCW  X

CPW   X,#0x40B8 ; check if we had reached the end of initialization range

JRC   ContinueInit

LDW   X,#0x47FF ; p = EEPROM_END

LD    A,#0xAA ; update showing initialization completed

LD   (X),A

NOP

NOP

BSET  _FLASH_IAPSR,#3 ; lock data eeprom write access

InitComplete:

callf f_main ; execute main

i hope the procedure is correct, please advice if something is wrong in this code. This is done before invoking main function.

Couldn't follow the FLASH_IAPSR changes in this windows as well. It shows "intrusive read" 

Thanks

[AA1]

The source of MCU reset can be detected by reading register RST_SR.

The bit DUL (FLASH_IAPSR bit 3), means EEPROM write is unlocked when bit is 1. And for you EEPROM write is unlocked when bit is 0. This is wrong.

See RM0016 page 45:

Before starting programming, the application must verify that the DATA area is not write protected by checking that the DUL bit is effectively set. The application can choose, at any time, to disable again write access to the DATA area by clearing the DUL bit.

After you write the unlocked keys, you MUST wait bit DUL is 1. Any you continue without any test.

This is also wrong, 'BSET _FLASH_IAPSR,#3' should be 'BRES _FLASH_IAPSR,#3

Also read PM0051.

And we must start with a simple program.

[DMega.1]

Thank you for the clarification. I am sorry for misunderstanding the manual. Now i had updated the assembly code

BSET  _FLASH_CR1,#0

BSET  _RST_SR,#0

BSET  _RST_SR,#3

BTJT  _FLASH_IAPSR,#3,unlocked

MOV   _FLASH_DUKR,#0xae

MOV   _FLASH_DUKR,#0x56

unlocking:

BTJF  _FLASH_IAPSR,#3,unlocking

unlocked:

    LDW   X,#0x47FF ; p = EEPROM_END                  

    LD    A,(X)         

    CP    A,#0xAA

After the changes the bit DUL (FLASH_IAPSR bit 3), means EEPROM write is unlocked is always '0'

[AA1 · Accepted solution]

After the changes the bit DUL (FLASH_IAPSR bit 3), means EEPROM write is unlocked is always '0'.

If you terminate with 'BRES _FLASH_IAPSR,#3 ;', bit is 0

On the last byte, address 0x47FF, after writing 0xAA you are not waiting for EOP.

A simple program is:

1. Enable write access to EEPROM

2. Test DUL bit

3. Write one byte to EEPROM

4. Wait EOP

5. Disable write access to EEPROM

6. Read EEPROM to confirm if write ok

[DMega.1]

Thanks for your clarification once again. I did try to run the above assembly program without single step / debug mode and then noticed the changes to the EEPROM write is working as expected.

The DUL bit is checked before writing to EEPROM and EOP is checked after a write operation to ensure programming is successful. 

Cheers