Wrong code generated on dual-core stm32h747, M4 side

[cberg.1]

I want to generate an interrupt on the rising edge of PI0 on the M4 CPU.

Unfortunately, when I program the GPIO With ARM Cortex-M4 pin context assignment, the code generated is as follows in gpio.c:

  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_0;
  EXTI_InitStruct.Line_32_63 = LL_EXTI_LINE_NONE;
  EXTI_InitStruct.Line_64_95 = LL_EXTI_LINE_NONE;
  EXTI_InitStruct.LineCommand = ENABLE;
  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_RISING;
  LL_EXTI_Init(&EXTI_InitStruct);

and in stm32h7xx_it.c:

void EXTI0_IRQHandler(void)
{
  ...
  if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
  {
    LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
    ...

But this is incorrect because while both init + IRQ executes on the M4, it programs the M7 interrupts delivery.

The correct way to make it work is to replace the following is the code above:

• LL_EXTI_MODE_IT => LL_EXTI_MODE_C2_IT

• LL_EXTI_IsActiveFlag_0_31() => LL_C2_EXTI_IsActiveFlag_0_31

• LL_EXTI_ClearFlag_0_31 => LL_C2_EXTI_ClearFlag_0_31

[Mahmoud Ben Romdhane]

Hello @cberg.1 ,

First let me thank you for posting and welcome to the ST Community.

Your request is under investigation, and I will get back to you ASAP.

Thanks.

Mahmoud.

[Mahmoud Ben Romdhane · Accepted solution]

Hello @cberg.1 ,

I escalated the problem to CubeMX team in an internal ticket (ID : 168700 ) to take a closer look at this issue.

(PS: ID 168700 is an internal tracking number and is not accessible or usable by customers).

Thanks.

Mahmoud.

[cberg.1]

I don't know the status of your internal bug, but I want to note that:

On version Version: 1.16.0 of STM32CubeIDE, I see that half the bug has been fixed.

• In stm32h7xx_it.c, EXTI0_IRQHandler is generated correctly, with LL_C2_EXTI... functions. Good!
• In gpio.c, the code is still wrong, and use LL_EXTI_MODE_IT instead of LL_EXTI_MODE_C2_IT.

Cedric