STM32CubeMX I2C Timing Register Calc Wrong?

[Robert Ritchey]

Posted on March 30, 2018 at 00:30

I was looking at the timing value that STM32CubeMX calculated for the I2C timing register in my STM32F486.  I have the I2C1 clock in at 80MHz.  I checked the data sheet and did not see a maximum value for the I2CCLK and CubeMX is not complaining so I figured it was OK to leave this as is.  When I checked the value for I2C_TIMINGR that CubeMX calculated it seems to be off somewhat.  The value for SCLH is 0x9C and the value for SCLL is EC.  If I back these out to actual time SCLH is 3.925usec and SCLL is 5.925usec.  The I2C clock turns out to be 100502.5Hz, just over the maximum 100KHz it should be.  It seems to me that these values really should be 0x9E and 0xEE.  Am I missing something here?  Thanks.  

#stm32f486 #i2c-timing-register #stm32cubemx #i2c-setup

[Jeff Tenney]

On the L4+, the I2C controller uses 2-3 clock cycles to synchronize before starting the SCLH or SCLL timers. Since the minimum sync is 2 cycles, CubeMX gives your expected values minus 2. Maybe it's the same on your F486.