SPI-receiver gets out of sync?

[HMüll.4]

Hi,

I'm using a STM32H523CC to receive 24 bit data frames via SPI. The SPI acts as receiver-only and is configured as follows:

Within my application I do not make use of the HAL-functions but have overwritten the SPI2_IRQHandler(). There I continuously read the data from the SPI RXDR register as soon as the SPI_FLAG_RXP is set. When some overflow/error-flags are set, they are cleared:

void SPI2_IRQHandler(void)
{
#ifdef USE_IRQ
   const uint32_t trigger2=SPI2->SR;
   if ((trigger2 & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR|SPI_FLAG_RXP)) != 0UL)
   {
      if ((trigger2 & SPI_FLAG_RXP) != 0UL)
       handleRxc(); // reads from SPI2->RXDR

      /* SPI Overrun error interrupt occurred ----------------------------------*/
      if ((trigger2 & SPI_FLAG_OVR) != 0UL)
      {
         __HAL_SPI_CLEAR_OVRFLAG(&hspi2);
      }

      /* SPI Mode Fault error interrupt occurred -------------------------------*/
      if ((trigger2 & SPI_FLAG_MODF) != 0UL)
      {
         __HAL_SPI_CLEAR_MODFFLAG(&hspi2);
      }

      /* SPI Frame error interrupt occurred ------------------------------------*/
      if ((trigger2 & SPI_FLAG_FRE) != 0UL)
      {
         __HAL_SPI_CLEAR_FREFLAG(&hspi2);
      }

      /* SPI Underrun error interrupt occurred ------------------------------------*/
      if ((trigger2 & SPI_FLAG_UDR) != 0UL)
      {
         __HAL_SPI_CLEAR_UDRFLAG(&hspi2);
      }
   }

The sender is submitting a permanent stream of data with 100000 frames per second (means 300000 bytes per second). This works fine and smooth in DEBUG and RELEASE build except for one situation:

When I power both, the sender and my STM32H523CC-based receiver at the same time, the SPI-reception gets out of sync. As I'm not connected with the debugger in this situation, I can not see what data are received exactly, but from what the result looks like, I have the feeling, the received data are shifted by one or two bytes so that my 24 bit frames are mixed/shifted into each other.

So my question: when I work with the NSS-signal, shouldn't this ensure some synchronisation? Means shouldn't the MCU recognise the start of a frame by NSS going to LOW and when NSS goes back to HIGH, shouldn't it end the frame here and make the received (partial) data available in RXDR while reception starts from the beginning?

Or asked in other way: assumed, NSS goes to LOW, then for some reason only 16 bits are received when NSS goes to HIGH, shouldn't the next time NSS goes to LOW the received data be part of the next frame? I would expect in this case the first 8 bits of the next frame are NOT made part of the previous one?

So how can I ensure the synchronisation to real 24 bits in one received frame works properly?

Thanks!

[TDK]

Yes, if NSS is used and goes high between words, the master and slave will sync. Is that happening? Can you show a trace of the SPI signal?

Sending in a stream of known data and then printing out the received data and comparing the two would yield some insights. It sounds like you're not quite sure what is going on.

Instead of silently ignoring errors, you should be setting a flag and indicate in some manner that they are happening.