I2C rise and falltime setting

[Sebastian33]

We have a board with a stm32u5. were VDDIO are connected to 1.8 V and  the I2C bus have pullup to 3.0 V. Some I2C devices uses 3.0 V logic levels and som 1.8 V. 

Between which voltage levels shall i measure the rise and falltime that i enter in cubemx. 

30%->70% of 1.8 V or 3.0 V .

We have possibility to turn off and on some devices on the bus that changes the rise and falltime on the bus. Shall then the longer or shorter rise/falltimes be used?

One reason we are asking is that our design engineers wonder why the signal of the clock never is piece wise equal in on and off timing as it is the case with other I2C masters

[FNiel.1]

Yes, it is standard regarding the slope, but I'm referring to the on/off timing (purple arrows). They are usually more towards the same timing (1/2) on a I2C clock. The UM10204 is with the 0.6uS minimum Thigh taking into account the timing above 70% level and that is with this signal on the limit of being compliant (green arrows). If the on/off timing (purple) was more equal then the high pulse would be more in compliance.

[FNiel.1]

See answer to Andrew.

[TDK]

> They are usually more towards the same timing (1/2) on a I2C clock.

The specification I showed above shows the requirement is about 1/3 vs 2/3, not 50/50. You are chasing a problem that doesn't exist (1V8 vs 3V3 voltage level difference notwithstanding).

[FNiel.1]

I'm totally inline with that the standard does not state any requiremnent for the on off ratio. We are making low power devices here and would like to have the lowest possible pull-up current and still be over 0.6uS Thigh. If the ratio could be closer to 1/2 on/off ratio then we would not need to raise the current.

Anyway, let's see if we can get this with the I2C timing register as proposed by Mholl.2

[MHoll.2]

To be 100% compatible with the standard (UM10204 from NXP, ex Philips), Your rise time on SDA and SCL should be < 300ns (from 30% to 70% Vdd), if You are using Fast-mode:

[FNiel.1]

You are right and we are also on the limit there and more 1/2 on off relation wont help there.

[Andrew Neil]

---

@FNiel.1 wrote:

We are making low power devices here and would like to have the lowest possible pull-up current

---

But you still need sufficient pull-up current to give a usable rise time.

Remember that the pullups only pass current while the line is low...

[Sebastian33]

Thanks by manuallyh adjusting SCLL bits im able to get closer to 400 kHz.