I2C rise and falltime setting

[Sebastian33]

We have a board with a stm32u5. were VDDIO are connected to 1.8 V and  the I2C bus have pullup to 3.0 V. Some I2C devices uses 3.0 V logic levels and som 1.8 V. 

Between which voltage levels shall i measure the rise and falltime that i enter in cubemx. 

30%->70% of 1.8 V or 3.0 V .

We have possibility to turn off and on some devices on the bus that changes the rise and falltime on the bus. Shall then the longer or shorter rise/falltimes be used?

One reason we are asking is that our design engineers wonder why the signal of the clock never is piece wise equal in on and off timing as it is the case with other I2C masters

[Andrew Neil]

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@Sebastian33 wrote:

the I2C bus have pullup to 3.0 V. Some I2C devices uses 3.0 V logic levels and som 1.8 V. ?

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Surely, that cannot work ?

The 1.8V devices need to be on a 1.8V bus ?

In any I2C bus, the master needs to be configured to a setting that will work for all slaves on the bus.

[TDK]

If the master is at 1.8 V, they should be the rise/fall times for 1.8 V. These setting shouldn't matter much.

A pin in open-drain mode pulled up to 3 V externally will work just fine here on a 1.8 V bus on the STM32 side.