I was trying out CubeMX for an STM32H753 part and noticed in the Clock Configuration tab that the DIVP1 drop-down can not be set to 1. Shouldn't this be possible?

[DMcGo.1]

According to the reference manual the DIVP1 field of the RCC_PLL1DIVR register should be possible to set to 0 meaning divide by 1. And in fact I have manually used this configuration in my project in order to get a 480 MHz output from PLL1 and it works fine to set this field to 0. Is this an oversight in CubeMX?

[TDK]

I would argue the RM is ambiguous here. Certainly the number 1 is odd. Maybe it considers a divisor of 1 not an actual divisor and so it's allowed.

[DMcGo.1]

I interpreted it as meaning 1 was allowed since otherwise in the table "0000000: ....." should state "Not allowed" like it is below for 0000010. I used this setting for two different parts now (STM32H743 and STM32H753) and it works fine. 12M crystal, multiplier 40 and divisor 1 to get a 480 MHz system clock (frequency verified). This is in a project not using CMSIS or CubeMX.

[JMate.2]

It appears that there is an inconsistency between the reference manual and ST's peripheral library. The STM32H753 reference manual does say that you are allowed to set DIVP to 0 for a divide value of 1:

However, the comment to the function for setting the PLL1 P Coefficient says that this is not allowed on the STM32H753 family line. From stm32h7xx_ll_rcc.h:

/**
  * @brief  Set PLL1 P Coefficient
  * @note   This API shall be called only when PLL1 is disabled.
  * @rmtoll PLL1DIVR        P1          LL_RCC_PLL1_SetP
  * @param  P parameter can be a value between 2 (or 1*) and 128 (ODD division factor not supported)
  *
  * (*) : For stm32h72xxx and stm32h73xxx family lines.
  */
__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)
{
  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P-1UL) << RCC_PLL1DIVR_P1_Pos);
}

Hopefully ST can provide some clarification.