How to map OCTOSPIM to port G on STM32U5Axxx

[MikeStrom]

I'm new to STM32CubeMX and have difficulties finding out how to map all OCTOSPIM_P2 signals to Port G. I can manually map some signals to Port G (CS, IO[7:4], DQS), but can't figure out how to map the rest. 

Any help most welcome!

[KDJEM.1 · Accepted solution]

Hello @MikeStrom,

I recommend you to refer to the STM32U5A datasheet and precisely Table 27. STM32U5Axxx pin/ball definitions and check whether you are able to map all OCTOSPIM signals to port G or not??

For example,  OCTOSPIM_P1_CLK signal is not available on port G.

Also you can used search method to find the availability of signal on different pins as shown in the below figure

I hope this help you.

Thank you.

Kaouthar

[MikeStrom]

Thanks for the feedback @KDJEM.1

It appears that it is not possible when reading Table 27. However, that means that the text in para 3.28 is a bit misleading:

Since we consequently are forced to run the entire CPU on 1V8, is it correct that we can run the OSPI clock at 93MHz in both SDR and DDR mode, effectively reaching 93MT/s and 186MT/s with 8 lanes? It looks possible to me from the data sheet, but I might have overlooked something. 

Thanks!

[Tesla DeLorean]

>>effectively reaching 93MT/s and 186MT/s with 8 lanes?

Some how I think that's probably super optimistic, and ignores achievable burst lengths, overhead and latency.

In OCTOSPIM nomenclature I think full I/O matrix means mapping of high/low banking. Perhaps allowing for interchange of CLK, NCS, DQS, IO's from P1 to/from P2

Although I don't see a OCTOSPIM CLK for either bank on GPIO-G

Can VCCIO be 3V3 if the rest of the MCU is at 1V8 ?

[KDJEM.1]

Hello @MikeStrom,

The OCTOSPI I/O manager is a low-level interface that enables an efficient OCTOSPI pin assignment with a full I/O matrix (before alternate function map) and multiplex of single/dual/quad/octal SPI interfaces over the same bus. 

That means the OCTOSPI I/O manager matrix allows the user to set a fully programmable premapping of functions:
• Any OCTOSPIM_Pn_CLK / OCTOSPIM_Pn_NCLK pair can be mapped independently to OCTOSPI1_CLK/OCTOSPI1_NCLK or OCTOSPI2_CLK/OCTOSPI2_NCLK
• Any OCTOSPIM_Pn_DQS can be mapped independently to OCTOSPI1_DQS or OCTOSPI2_DQS
• Any OCTOSPIM_Pn_NCS can be mapped independently to OCTOSPI1_NCS or OCTOSPI2_NCS
• Any OCTOSPIM_Pn_IO[3:0] and OCTOSPIM_Pn_IO[7:4] can be mapped independently to OCTOSPI1_IO[3:0], OCTOSPI1_IO[7:4], OCTOSPI2_IO1[3:0] or OCTOSPI2_IO[7:4]

For more information, I recommend you to look at RM0456 and precisely section 29.4 OCTOSPIM functional description

This sentence means that it’s possible to use OCTOSPIM pin port 1 for OCTOSPI2 and OCTOSPIM pin port 2 for OCTOSPI1.

The values are shared in table 140. table141. and table 142. are obtained on such conditions:

Unless otherwise specified, the parameters given in Table 140 to Table 142 are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Delay block enabled for DTR (with DQS)/HyperBus
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1 unless otherwise specified

For that, I advise you to refer to the datasheet and check the conditions.

I hope this answers your request.

Thank you.

Kaouthar