2019-05-08 08:03 AM
I had several projects running, created with STM32CubeMX. Among them also the example H743ZI_LwIP_test1. Things were fine with firmware 1.3.0 and 1.3.2 but after upgrading to 1.4.0 , I can no longer connect to the network. No ping, no nothing. Currently I test with the NUCLEO-H743ZI board.
I compared .ioc files and various code source, but couldn't find any
Any help welcome,
thanks in advance
Peter
Solved! Go to Solution.
2020-01-06 05:58 AM
Can anyone send example project ? thanks so much Cubemx 5.4
2020-02-13 05:28 AM
An Update to this
As I initially wrote that problem occurred with the H7 firmware update from FW_H7_V1.3.0 to FW_H7_V1.4.0. After being busy with other projects I resumed MCU programming still with the H7 family and meanwhile CubeMX is at V5.5 and H7 firmware at FW_H7_V1.6.0.
Good News the above problem seems gone.
When comparing the code generated now to before one finds some differences in the ethernetif.c file, the relevant to me seems in function low_level_input(...) :
old code:
#if defined(DUAL_CORE) && defined(CORE_CM7)
/* Invalidate data cache for ETH Rx Buffers */
SCB_InvalidateDCache_by_Addr((uint32_t *)RxBuff.buffer, framelength);
#endif
new code:
#if !defined(DUAL_CORE) || defined(CORE_CM7)
/* Invalidate data cache for ETH Rx Buffers */
SCB_InvalidateDCache_by_Addr((uint32_t *)RxBuff.buffer, framelength);
#endif
As you can see the #if has changed resulting that the call to SCB_InvalidateDCache_by_Addr is now active while it wasn't before.
My guess is that the ST programmers made a mistake when adapting the template file (ethernetif_h7.ftl) for the dual core H7x5x and later corrected it.
BTW: when using the ADCs again SCB_InvalidateDCache_by_Addr() is a good friend to make the DMA mode working.
2020-02-13 01:44 PM
SCB_CleanInvalidateDCache is inappropriate. Piranha's post below explains this well. For H7_FW V1.5.0/V1.6.0 refer https://community.st.com/s/question/0D50X0000C6eNNSSQ2/bug-fixes-stm32h7-ethernet.
2021-08-05 08:12 AM
Is this "data cache impacting ethernet" also applicable to 32F417?
I am working on a project on which a huge amount of time has been spent applying every ST bug patch found by googling around :) and it would be great to know if this applies. The current CPU config is: data cache, instruction cache, and prefetch are all ENABLED.
2021-08-07 03:11 AM
The cause for my original question was exclusively 32H... related, it occured after I switched from a 32F746 to the above H nucleo board. There was nothing noticeable with an F board using Ethernet (it has a different memory-architecture), in other words everything worked as documented.
However, I haven't done any further development for more than a year, so I can't say what new bugs ST managed to implement in their firmware.