cancel
Showing results for 
Search instead for 
Did you mean: 

How to enable Flash Instruction prefetch for a STM32H562 in CubeMX?

MMeie.3
Associate II

Hi

For other STM32 (I checked a STM32L452 and STM32F469) I could enable the Flash Instruction prefetch by setting “Prefetch Buffer” to “Enabled” in the RCC settings. This then set PREFETCH_ENABLE to 1 in stm32F4xx_hal_conf.h.

MMeie3_0-1744271642265.png

The STM32H562 also as a Prefetch Buffer, but I cannot find the “Prefetch Buffer” option in CubeMX , and PREFETCH_ENABLE is always 0. Was the “Prefetch Buffer” moved or is it missing?

As a work around I can manually call __HAL_FLASH_PREFETCH_BUFFER_ENABLE(), but having the option back would still be nice.

I use STM32CubeMX Version 6.14 with the Firmware Package V1.5.0 to generate a STM32CubeIDE project on Windows 11.

MMeie3_1-1744271735322.png

 

3 REPLIES 3
mƎALLEm
ST Employee

Hello,

I'm escalating this internally and I will get back to you with any feedback (internal ticket 207309 not accessible by community members).

Thank you for your patience.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

Hello @MMeie.3 ,

The Prefetch enable buffer option is indeed missing in STM32CubeMx. It will be fixed in the coming revisions of the tool.

Thank you for your contribution. 

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

Dear ST-Staff,

I didn't notice existence of PrefetchBuffer on STM32H5 until this topic.

I updated my NUCLEO-H563ZI example project with PrefetchBuffer enable.

Here is piece of a sample,I put PrefetchBuffer enable routine after SysClock ramp-uped.

/**************************************************************************/
/*!
    @brief	Configures Main system clocks & power.
	@brief  System Clock Configuration
          The system Clock is configured as follows :
             System Clock source            = PLL (HSE:8MHz)
             SYSCLK(Hz)                     = 250000000
             HCLK(Hz)                       = 250000000
             AHB Prescaler                  = 1
             APB1 Prescaler                 = 1
             APB2 Prescaler                 = 1
             PLL_M                          = 4
             PLL_N                          = 250
             PLL_P                          = 2
             PLL_Q                          = 5
             PLL_R                          = 2
			 PLL_FRACN                      = 0
             Flash Latency(WS)              = 5
	@param  None
	@retval None
*/
/**************************************************************************/
static void SystemClock_Config(void)
{
	RCC_OscInitTypeDef RCC_OscInitStruct = {0};
	RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
	
	/** Configure the main internal regulator output voltage
	*/
	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
	
	while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
	
	/** Initializes the RCC Oscillators according to the specified parameters
	* in the RCC_OscInitTypeDef structure.
	*/
	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
	RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL;
	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
	RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;
	RCC_OscInitStruct.PLL.PLLM = 4;		/* HSE:8MHz/4 = 2MHz */
	RCC_OscInitStruct.PLL.PLLN = 250;	/* 2MHz*250 = 500MHz */
	RCC_OscInitStruct.PLL.PLLP = 2;		/* 500MHz/2 = 250MHz */
	RCC_OscInitStruct.PLL.PLLQ = 5;		/* 500MHz/5 = 100MHz (for SDMMC/SPI) */
	RCC_OscInitStruct.PLL.PLLR = 2;		/* 500MHz/2 = 250MHz */
	RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1;
	RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
	RCC_OscInitStruct.PLL.PLLFRACN = 0;
	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
	{
		for(;;){
			__NOP();
		}
	}
	
	/** Initializes the CPU, AHB and APB buses clocks
	*/
	RCC_ClkInitStruct.ClockType 	 = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
								      |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
								      |RCC_CLOCKTYPE_PCLK3;
	RCC_ClkInitStruct.SYSCLKSource 	 = RCC_SYSCLKSOURCE_PLLCLK;
	RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;	/* SYSCLOCK :250MHz */
	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;	/* PCLK1    :250MHz */
	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;	/* PCLK2    :250MHz */
	RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;	/* PCLK3    :250MHz */
	
	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
	{
		for(;;){
			__NOP();
		}
	}
	
	/* If Latency is at least one wait state,then set prefetch buffer enable to improve performance! */
    if (__HAL_FLASH_GET_LATENCY() != FLASH_ACR_LATENCY_0WS)
    {
		if(!(FLASH->ACR & FLASH_ACR_PRFTEN)) {
			__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
		}
    }
	
	/* I/O Compensation for fast interface(OCTO-SPI,SDMMC,SPI,SAI). */
	/* Activate CSI clock mandatory for I/O Compensation Cell*/
	__HAL_RCC_CSI_ENABLE() ;
	/* Enable SBS clock mandatory for I/O Compensation Cell */
	__HAL_RCC_SBS_CLK_ENABLE() ;
	/* Enables the I/O Compensation Cell */
	HAL_SBS_EnableVddIO1CompensationCell();
	HAL_SBS_EnableVddIO2CompensationCell();
}

Entire my project for NUCLEO-H563ZI is here.

To be honest, thanks to strong I-Cache,
the PrefetchBuffer enabled effect is not felt so much(THIS IS A INDIVIDUALLY THOUGHT).
Anyway,works stable for week.I like H5.
I'll research more detail and report on my blog in the future.

Best regards,
Nemui.