HAL_ADC_Start_DMA acquire only a subset of channels

[Fede Rico]

Posted on September 22, 2017 at 09:46

Hi there,

i'm working on a STM32F103 MCU and I want to acquire 9 channels with ADC1.

With STM32Cube I configured the ADC1 in this way:

• Scan conversion mode: Enabled.
• Enable regular conversion: Enable.
• Number of conversion: 9

These is the channel list:

1. Vref Int
2. Temperature Sensor
3. IN8

4. IN9

5. IN10

6. IN11
7. IN12
8. IN13
9. IN15

Also I configured the DMA to transfer the data from the ADC to a memory buffer.

• Mode: Normal
• Increment Address: Memory
• Data Width: Word

To start the conversion I use:

HAL_ADC_Start_DMA( ADC1_ModuleHandler, ADC_1_Buffer, ADC_1_CH_MAX_VALUE )

Where:

• ADC1_ModuleHandler: ADC Handler.

• ADC_1_Buffer: uint32_t array with 9 elemets.

• ADC_1_CH_MAX_VALUE: enum to identify the channel. It starts from 0 to 9.

The conversion works fine but into the ADC_1_Buffer only the first five elements contain a value different from 0. the other 4 elements contain 0.

Moreover if I convert to analog voltage the value of the first element ( Vref Int) I obtain 1.2V that correspond to the internal Vref. So I think that the ADC conversion works.

I don't know why only a subset of channels is converted.

Do I missing some configuration parameters?

Thanks in advance!

Federico

#dma-adc #scan-mode #stm32cubemx(hal) Note: this post was migrated and contained many threaded conversations, some content may be missing.

[Fede Rico]

Posted on September 26, 2017 at 16:19

I fix the problem!

The problem was into the data with of the peripheral. I set 'Word' but the ADC data with is 'Half Word'.

The memory data with remains a 'Word'.

Now the buffer value make sense.

[Vangelis Fortounas]

Posted on September 26, 2017 at 18:25

Hello Ben !

The DMA is configured for word access , yes.

And the array[] is 32bit array.

But when use  array[0] or array[1]  ...etc  to read the results , the value you read is 32bit and includes the next word readed from DMA

Regards

vf

[Ben K]

Posted on September 27, 2017 at 11:14

This is not true. If the MSIZE is set to word aligned, and the MINC bit is set, the memory address register of the DMA will be incremented by 4 after each transfer. Therefore there will be the result of exactly one transfer in each word of the array.

[Vangelis Fortounas]

Posted on September 27, 2017 at 14:39

Hi again Ben

I totaly agree with you.

I had in my mind that 

Data Width: Word

  means 16 bits   because F1 has 12 bits ADC and i missed the point  (this was the tricky part from the begining of the post). Of course it was false.

The answer was based on the above fact.

[Fede Rico]

Posted on September 27, 2017 at 14:42

Data width 'Word' means 4 byte. The 12-bit ADC has data width 'Half-Word'. So the DMA configuration had two different width setting: 'Half Word' for the peripheral and 'Word' for the memory.

[Vangelis Fortounas]

Posted on September 27, 2017 at 15:55

Data width WORD is processor dependant. For theese processors is

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0274b/index.html

. (it's written in UM, in glossary)