Clock Configuration Setting on STM32H750B-DK (post TGFX project generation)

[Al-E-Bags]

Hi.  I am working with the above H750B discovery board developing a touch gui for my project.  I am still at the very early stages of design.   I have imported the project into CubeIDE  and I have started to implement the required user code for the existing screen widgets and so far all is good (everything is working as it should).  I now want to enable the boards SPI and USART peripherals as the H750B will eventually have to communicate with the projects additional MCU's (STM32411RE) via the H750B's gui. 

The unmodified TouchGFX STM32H750B-DK.ioc clock configuration screen is presumably set optimally via TouchGFX Generator however, adding SPI1 as a peripheral in CubeIDE generates clock issue errors.  Using the auto resolve option the result knocks the SPI1,2,3 Clock Mux and SYSCLK down to 75MHz. I assume that 75MHz is the maximum speed at which the SPI peripheral can operate?

I'm wondering how to reset the SYSCLK back to it's unmodified 480MHz state without introducing a bunch of timing issues across the rest of the project?  I ask because I don't want to 'break' stuff that is currently working. 

Is there any particular reason why I sould not 'Migrate' when opening the *.ioc file from TouchGFX from within the IDE?  Thus far I have opted to 'Continue' in order to keep compatibility with the TouchGFX project version.   

TouchGFX v4.24.1, CubeIDE v1.16.1.  

Thanks for any advice on these matters.

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[SofLit · Accepted solution]

Hello,

This subject is more related to CubeMx than to TouchGFX.

In fact, enabling SPI1,2,3 at VOS0 (because the system clock is already set to 480Mhz).

According to the user manual, SPI1,2,3 kernel clock should not exceed 200MHz as shown by the pop-up:

And this is confirmed by the reference manual RM0433:

So what I suggest to keep the system clock at 480MHz (VOS0) is to select another kernel clock source for SPI1,2,3. For example you can use PLL2P as a clock source for SPI1,2,3: 

Hope that answers your question.

[Al-E-Bags]

Ah! I see.  If I select /6 DIVM2 and X96 DIVN2 and leave DIVP2 at /2, I reach exactly 200 MHz on the SPI1,2,3 Clock Mux using PLL2P as the source.  Would it be adviseable to knock it back from the 200 MHz maximum as a precaution?   Thanks for your help.   

[SofLit]

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@Al-E-Bags wrote:

Ah! I see.  If I select /6 DIVM2 and X96 DIVN2 and leave DIVP2 at /2, I reach exactly 200 MHz on the SPI1,2,3 Clock Mux using PLL2P as the source.  Would it be advisable to knock it back from the 200 MHz maximum as a precaution?   Thanks for your help.   

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Here you are speaking about PLL2 parameters?

If yes, 200MHz is the maximum and you can decrease it and if you don't have any warning/errors in CubeMx you can go ahead ..

[SofLit]

@Al-E-Bags 

Need to accept the comment that answered your original question.

I change it then ..

[Al-E-Bags]

sorry, my bad! :)