What exactly starts the clk during spi communications?

[Iviti.1]

According to section 28.9.1 (of RM0091), the spi communications are enabled when register 6 is active (SPE set to 1). According to the rm0091 guide, once the spi communications are active, and register 14 is set to 0 (receive only mode) then the clk pin should start up. But when I pause the debugger at that stage, I can see both those pins be in the correct setting, but sometimes the clock is on and sometimes it is not on. So what exactly starts the clk during spi communications?

I dont know if it matters, but I am connected in half duplex master mode to an spi compatible chip (ssc). I am using an stm32f042k6t6 chip on a nucleo board.

[Nikita91]

What means "register 6 is active" ? You mean SPE bit in CR1 register ?

The clock starts when something is written in the DR register and stops at the end of this data transmission.

[Iviti.1]

I disagree that the clock starts when something is written in the DR register, at least during the receive stage. on line 1072 of stm32f0xx_hal_spi.c, it states:

 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 
 {
 
  /* Enable SPI peripheral */
 
  __HAL_SPI_ENABLE(hspi);
 
 }

In other words , check if spi is enabled, if it's not, then enable it. But If I remove the "if" section and just tell it to enable spi no matter what, then it starts the clock at that point. Yet I have not started writing to the dr register. Also, on receive, the external (slave) chip doesnt know to start sending until clk is active.

[waclawek.jan]

Read out and check/post the SPI registers content just before that line.

JW

[Nikita91]

As the clock runs only when the master has something to transmit, check if the TX FIFO is empty when you enable the SPI setting SPE bit.

[Iviti.1]

the contents of CR1 are 1000001101011101

Where the 14th bit is 0 (receive mode) and the 6th bit is 1 (SPI active)

[Iviti.1]

If the clock only runs when master needs to transmit, how does it receive messages? In other words, how does the slave transmit with no clock?

[waclawek.jan]

And other SPI registers?

CR1 appears to be OK, there may be some internal state though which prevents the clocks, to which it arrived through previous history; so we need to know about that history. Maybe there's also some hardware dependency.

Please prepare a minimal but complete compilable example exhibiting the problem; best without using any "library" such as Cube.

JW

PS. @Nikita91​ , the SPI is here set to bidirectional mode (halfduplex, CR1.BIDIMODE=1), when you turn it into Rx, it ought to clock automatically.

[Iviti.1]

Ok, So I checked all of the spi registers (cr1,cr2,sr,both i2c, and all 3 crc). Only CR1 changes between cycles:

1. CR1 = 831d (spe off, receive mode)
2. hal transmit
3. CR1 = c35d (spe on, send mode)
4. hal receive
5. CR1 = 835d (spe on, receive mode)
6. (next cycle)
7. CR1 = 835d (spe on, receive mode)
8. hal transmit
9. CR1 = c35d (spe on, send mode)
10. hal receive
11. CR1 = 831d (spe off, receive mode)
12. (start over)

What is strange is that before we go into receive mode both times, all of the registers are in the exact same states. Yet in one cycle, it remembers to turn on the CLK and the other one it does not.

Ill work on a minimal example, but it's as minimal as it gets (hal spi transmit, then hal spi receive). Delays if you want them but they dont change anything.

[waclawek.jan]

I don't use Cube/HAL so you may perhaps extract the relevant lines from it and insert it into your code directly.

JW