2026-02-16 12:52 PM - last edited on 2026-02-17 3:39 AM by mƎALLEm
Previously, I used this delay function in inline assembler in my projects (on Cortex M3, M4):
static inline void delay_m4(uint32_t cnt){
asm volatile(
"1: SUBS %0,#1" "\n\t"
" bne 1b"
:"=r" (cnt)
: "0" (cnt)
);
}
Now I'm trying to add this function to a project on a Cortex M0+ microcontroller (STM32G0XX).
The compiler gives me this error message:
Error: instruction not supported in Thumb16 mode -- `subs r3,#1'
I'm sure this is a compiler error because:
1) the documentation for the Cortex M0+ "PM0223" lists the subs instruction as available;
2) looking through the assembly listings of other Cortex M0+ projects, I see that
the subs instruction is used constantly.
STM32CubeIDE
Version: 1.16.1
Build: 22882_20240916_0822 (UTC)
Solved! Go to Solution.
2026-02-16 1:29 PM
Unified syntax is required for the "subs" instruction:
static inline void delay_m4(uint32_t cnt) {
asm volatile(
".syntax unified \n\t"
"1: SUBS %0,#1 \n\t"
" bne 1b \n\t"
:"=r" (cnt)
: "0" (cnt)
);
}Dig more if you want:
M0 inline assembly: subs r0, #32 not supported - NXP Community
Directives that Change the Instruction Type — TI Arm Clang Compiler Tools User's Guide
2026-02-16 1:29 PM
Unified syntax is required for the "subs" instruction:
static inline void delay_m4(uint32_t cnt) {
asm volatile(
".syntax unified \n\t"
"1: SUBS %0,#1 \n\t"
" bne 1b \n\t"
:"=r" (cnt)
: "0" (cnt)
);
}Dig more if you want:
M0 inline assembly: subs r0, #32 not supported - NXP Community
Directives that Change the Instruction Type — TI Arm Clang Compiler Tools User's Guide