I'm confused by the power consumption estimate in STM32CubeIDE

[magene]

I'm starting a new STM32H7A3 project in STM32CubeIDE. I've got the peripherals assigned and would like to understand more precisely how each peripheral and things like CPU frequency affects current draw. When I first click on the Tools tab without changing any of the default settings, the run step current in 69.9 mA. If I drag the CPU Frequency slider from the default setting of 280 MHz to 90 MHz, I get a run step current of 7.9 mA. That's a decrease in current of almost 9X for a decrease in CPU frequency of about 3X. Seems like power should scale roughly linearly with clock frequency. And then when I drag the CPU frequency slider back up to 280 MHz, the run step current is 26.5 mA which is roughly 3X the 90 MHz value, about what I'd expect. I'm guessing the initial 69.9 mA value is just wrong but I could use some confirmation before I spin up a board.

[waclawek.jan]

The authoritative information is of course in the datasheet.

JW

[TDK · Accepted solution]

It looks like the default (70 mA) has cache enabled, and then when you drag the slider it disables those, so the current drops. If you move the current slider instead, you get some interesting behavior.

 

 

Current consumption should be roughly linear with frequency, but it will also depend on what else is enabled. LDO vs SMPS has a huge effect as well.

I would trust the datasheet over CubeMX. Lots of info in there about power consumption.

[magene]

@Community member​  and @TDK​ : Thanks for the very helpful and very quick answers. I'm working my way through the power supply section of the data sheet right now and was hoping to use the power calculator in the IDE as a way to check my understanding. My basic question is which of the power supply schemes is going to be most efficient for my battery powered application. The data sheet shows this relationship between LDO current and SMPS current

IDDSMPS = IDDLDO × (VCORE ÷ (VDD × efficiency))

So, if Vcore = VDD = 3.3VDC the IDDSMPS is greater than IDDLDO in all cases since the efficiency curves never get above about 90%. Which means to me the LDO on, SMPS off power scheme is going to be the most efficient. I'm hoping that is consistent with @TDK​ 's comment that "LDO vs SMPS has a huge effect"

I'd really appreciate if someone could confirm that LDO on, SMPS off is going to be the lowest power consumption power supply scheme all else being equal.

And thanks for pointing out the cache on/cache off issue. I sure didn't see it when I was running various scenarios.

Thanks again.

[TDK]

> if Vcore = VDD = 3.3VDC

VCORE is around 1.2V, but can vary based on your settings. It's never VDD.

In general, SMPS is more power efficient than the LDO in the same way that a buck converter is more efficient than an LDO. If it wasn't, nobody would bother with the complexity of a converter.

[magene]

Huge help, thanks very much.