Understanding STM32MP257FAI3 ETHSW Ports

[cjb80]

Hello,

I am working on a schematic for the STM32MP257FAI3 and the documentation seems to be inconsistent and/or incomplete regarding which ports go where with the built-in Ethernet switch.  The data sheet says ETHSW has three ports in which the "The third port is connected internally to the ETH1 controller". This implies that ETH2 and ETH3 are the external RGMII interfaces.

The "Getting Started with ... Hardware Development" guide says "ETH1 is either ETH1 direct or ETHSW port2" (it is unstated, but combined with the data sheet this would be an internal connection), and ETH3 there is a note "ETH3 is ETHSW port1".  There is no such note for ETH2, so this omission implies that ETH2 is not connected to ETHSW (or perhaps it is connected through STNoC??).  The block diagram in the data sheet also matches this notion.

In any case, it would be very helpful if there was a table that show what is connected to what when ETHSW is enabled.  At this point I need to know what pins to connect to PHYs, it seems like it is either ETH1 and ETH3 (hardware design guide is correct) or ETH 2 and ETH3 (data sheet is correct).

Thanks

[Olivier GALLIEN]

Hi @cjb80 ,

I know that ETH port mapping could be confusing.

Please have a look to wiki doc ETH internal peripheral - stm32mp25-beta-v5 

Let us know if it help 

Olivier 

[cjb80]

Hello,

To be honest, that link doesn't answer the question. 🙂 But I did find this link after digging around: https://wiki.st.com/stm32mp25-beta-v5/wiki/Ethernet_switch_overview

Based on the diagram, it looks like RGMII1 and RGMII3 are the two ports that connect to the switch and that internally GMAC1 is connected to the processor (the third port of the switch).  So I believe that the answer to my question is "RGMII1 and RGMII3 are the external connections to the switch".

Please let me know if you disagree. 

(Last night I thought that I should just hook up all of the ports so it pushes the problem to a later point in time)

Chris

[PatrickF]

Hi @cjb80 
I confirm your understanding. Please have a look to Reference Manual RM0457

What could be confusing is the assignment of ETHSW ports (port0, port1 and port2) wrt to names of the GMAC IP (ETH1) and names of the external pins (ETH1 and ETH3).

Regards.

[cjb80]

Hello Patrick,

I have nearly completed connecting all of the ports in my schematic and realized that there is no ETH3_MDIO, ETH3_MDC, and ETH3_RGMII_CLK125.

I assume for the MDIO and MDC, I need to connect the ETH1_MDIO and ETH1_MDC and then have a different hardware address for the ETH3 PHY.  Is that correct?

What should I do with the reference clock line? (CLK125)

(I am using the RTL8211F from the "Getting started with STM32MP25 Hardware ... " guide, if that matters)

Thanks,

Chris

[PatrickF]

Hi @cjb80 

don't know if you had got the STM32MP257F-EV1 evaluation board schematics (need to be register as early access customer on local sales office). Would help you to find answers to your concerns as this board has 3 x RTL8211F. The document is plan to became public by end of this month.

Anyway, I try to answer.

You should use ETH1_MDC/ETH1_MDIO for both ETH1 and ETH3 PHYs which must have different slave address (we use: ETH1 = 0x04, ETH3 = 0x05 and ETH2 = 0x01, even if the later is using a different MDIO bus). This is logical as MDIO is handled from the GMAC (ETH1 or ETH2) and not from the ETHSW.

The ETH3 PHY CLKOUT is left open in all cases as both ETH1 GMAC and ETHSW are using the same clock for all of their PHY interfaces, either internal 125MHz generation from RCC, or ETH1_CLK125 input pin.

Regards.

[cjb80]

I am working with an FAE now though the process has been slow to get the meeting and then now to get the NDA finalized.  That is in the works.  In any case, I don't have the schematic yet but I do have a board on order.

I was using a crystal for each PHY, can you tell me how the development board handles this?  I understood that the PHY needed to provide a clock to the MPU (via the clock output).  Since ETH1 and ETH3 would have two different PHYs, then I would assume that the clocks are not aligned. 

I know that the MPU can generate internal clocks, does it provide that clock signal out to each PHY (i.e., there is no crystal for each PHY?)?

I will need to refresh myself on the MDC/MDIO signals, but I think your comment sounds reasonable.

Thanks for getting back to me!

Chris