cancel
Showing results for 
Search instead for 
Did you mean: 

Unable to trigger Cortex-m4 from cortex-A7 in STM32MP157

Srikanth1
Associate III

Hello 

     We are using STM32MP157 in our custom board. 

     We are trying to trigger Cortex-M4 from Cortex - A7 BareMetal software.

     In this we generated cortex-M4 code in CubeMX and debugging with ST32CubeIDE and in debug it's working fine.

     we configured memory in cortex-M4 as per following

     MEMORY
     {
           RETRAM_interrupts (xrw) : ORIGIN = 0x00000000, LENGTH = 0x00000600
          SRAM1_text (xrw) : ORIGIN = 0x10000000, LENGTH = 128K
          SRAM2_data (xrw) : ORIGIN = 0x10020000, LENGTH = 128K
     }

     We take a .bin file of Cortex-M4 and triggered from Cortex-A7 BareMetal software, while triggered getting following observations

1) If SRAM1_text is < 64KB, it has triggered from Cortex-A7 and working fine.

2) If SRAM1_text is >64KB, it has not triggered from Cortex - A7 but it's it works when debug with ST32CubeIDE.

3) This Cortex-M4 project .elf file works in U-Boot while loading .elf file with rproc commands and with rproc start 0 ,it triggered.

   Here, our problem is, If SRAM1_text is > 64KB, we are unable to triggered from cortex-A7 BareMetal software.

   Can anyone help me in this regrads

regards

srikanth 

 

 

4 REPLIES 4
DBELL.1
ST Employee

Hello @Srikanth1 ,

 

The SRAM1 could be used somewhere else maybe for the heap or the stack.
Can you check your linker files and your start up files in both A7 and M4 projects?

 

regards,
David B.

Thank you for reply.

Actually, we used SRAM1 to text section in cortex-M4 only, not used in Cortex-A7.

As per our case <64KB SRAM1 file is triggered but >64KB SRAM1 file is not triggered from Cortex-A7.

 

regards

srikanth

PatrickF
ST Employee

Hi @Srikanth1 

Maybe cache issue, code copied from Cortex-A7 does not really flight completely up to SRAM1 (i.e. kept in cache).

Did you dump SRAM1 content from Cortex-M4 side with a debugger like CubeIDE (without loading code from the debugger).

Are you sure of the A7 bare-metal SW which copy the code to SRAM1 ?

Did you try copying SRAM1 from A7 RAM aliases (0x30000000) ?

Regards.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.
Srikanth1
Associate III

we are not enabling the cache at this time in both Cortex-A7 and Cortex-M4.

Actually, in cortex-A7 BareMetal code we are reading the data(.bin) from NORFLASH and write into Retram alias(0x38000000) and SRAM1 (0x10000000) according to the bin file.