STM32MP257 LPDDR4 routing: Line length from die to ball for STM32MP257 (VFBGA424 package)

[Fritz2]

Hi,

I'm working on layout routing from STM32MC257AAK(Package: VFBGA424) to LPDDR4 (32bit).

I have read the "Memory layout rules" in the App-Note AN5724.

For a good LPDDR4 signal timing it is usefull to do a "Line-Length-Matching" on the LPDDR4 signals, as noted in the AN5724.

Addidtionally:

For calculating a good "Line-Length-Matching" from MCU to the LPDDR4, I want to know the internal line length from die to ball (Package: VFBGA424).

Could you please provide the internal line length from die to ball (Package: VFBGA424).

Reguards

[Olivier GALLIEN]

Hi @Fritz2 

see in AN5724 following reference 

"The STMicroelectronics templates and the length equalization tables can be used to simplify the task of equalizing signal trace lengths. These tables include the trace lengths of the packages and can be obtained on Examples of DDR memory routing on STM32MP2 MPUs, available on www.st.com"

Information are available in this package you can download from here : 

https://www.st.com/en/microcontrollers-microprocessors/stm32mp257f.html#cad-resources

Olivier