Core1 Wake-up Issue During SD Card Boot on STM32MP257

[Aks]

Hello

We are currently attempting to boot both Cortex-A35 cores of the STM32MP257 processor using an SD card. While we have successfully verified that both cores function independently under bare-metal conditions, we are facing challenges in waking both cores during the SD card boot process.

Specifically, we are attempting to release Core 1 from reset by setting the C1P1RST bit in the RCC_C1P1RSTCSETR register. However, we observe that the reset does not get released as expected—the value of the register does not reflect the release of the reset.

We are following the sequence outlined in Section 3.4 "Cortex-A35 boot mode" of the STM32MP257 Reference Manual. In this context, we would appreciate further clarification on the following steps mentioned in the boot procedure:

2. The core requests a warm reset through its internal reset management register in secure mode.
3. Both cores enter in WFI state.

We request a detailed explanation of the above two steps, particularly with regard to:

• The mechanism by which a core requests a warm reset in secure mode.

• The significance and timing of both cores entering the WFI (Wait-For-Interrupt) state in relation to system boot and reset management.

Thanks & Regards

Akshitha Pattem

[PatrickF]

Hi,

I think you don't need to use C1P1RST as I understand from wiki that both CA35 cores are executing the same Flash code from FSBL (so both core are started at same time by the bootrom). You should manage the second core behavior by yourself (in our FSBL code, I think 2nd core is immediately parked in WFI, see here ). Maybe this will help you to implement your own FSBL (usually you need to use the core ID to branch different init for the two CA35 cores).

https://wiki.st.com/stm32mpu/wiki/STM32_MPU_ROM_code_overview#On_STM32MP2-lines_and_STM32MP2-lines

Regards,