Regarding Memory Read and Write in STM32MP257

[Aks]

Hello

We  are testing Memory read and Write in STM32MP257F-DK Board. We are not able to read or write into SRAM1 & SRAM2, but RETRAM and SYSRAM Works. We have enabled SRAM1EN & SRAM2EN in RCC_SRAM1CFGR & RCC_SRAM2CFGR respectively, but read and  write of memory doesn't work.

Thanks & Regards

Akshitha Pattem

[PatrickF]

Hi @Aks 

maybe precise more details:

which processor is doing the access ? Cortex-A35 or Cortex-M33 ?

For Cortex-A35, is it with a Linux driver or else ?

Which error message ?

Is RIF correctly setup ?

https://wiki.st.com/stm32mpu/wiki/Resource_Isolation_Framework_overview

Regards.

[Aks]

Hello @patrick F

We are currently evaluating both cores (Cortex-A35 and Cortex-M33) in a bare-metal environment and have encountered issues accessing the RAMCFG registers. Specifically, we are unable to perform read or write operations. Could you please confirm whether there is any default write protection mechanism enabled for these registers? 
Additionally, we are experiencing similar access issues with LPSRAM1, LPSRAM2, and LPSRAM3. Despite our attempts, read and write operations appear to be blocked.

In reference to the PWR backup domain control register 2 (PWR_BDCR2), the documentation states:

“Non-secure unprivileged write access only by CPU3. Any read access from CPU1, CPU2, and CPU3 is allowed to this register.”

Could you kindly confirm if this means that write access to PWR_BDCR2 is restricted exclusively to CPU3, and that CPU1 and CPU2 do not have write permissions under any condition?

Best regards,
Akshitha Pattem

[PatrickF · Accepted solution]

Hi,

maybe because you are trying to access SRAM1/SRAM2 in secure. Need to change default RISAB settings to your needs.

I think also that depending on boot mode, the BootROM might change default settings as well.

https://wiki.st.com/stm32mpu/wiki/STM32MP2_ROM_code_resource_isolation

I'm not expert on this, you should read reference manual and use CubeMx to define more finely your RIF related settings.

I confirm DBP in PWR_BDCR2 is only writable by CPU3 under any circumstances. This bit is to allow CPU3 to unlock backup domain resources access.

For control from CPU1 or CPU2, you should use DBD3P in PWR_BDCR1, which is somewhat equivalent.

Regards.