STM32MP133 OTP Alternate QSPI Boot

[Jasper]

Hello, In order to use the non-default QSPI boot locations, my understanding is port0-port3, 4 signals need to be defined in OTP words 3, 5, and 6 based on a similar question about SDMMC1 discussed here:

https://community.st.com/t5/stm32-mpu-products/how-to-change-emmc-interface/td-p/344994

For QSPI the default signals according to the getting started guide, AN5474, are:

PB2 QUADSPI_BK1_NCSQUADSPI_BK1_NCS
PF10 QUADSPI_CLK
PF8 QUADSPI_BK1_IO0
PF9 QUADSPI_BK1_IO1

What is the mapping for the OTP ports 0-3 to the functional signal names NCS, CLK, IO0, IO1?

i.e. port 0=NCS, CLK, IO0, or IO1? Same for the other three ports.

I was not able to find this described or an example for QSPI and OTP.

Thanks.

[Jasper]

Also, think I need the OTP port number mapping for QUAD SPI IO2 and IO3.

[PatrickF]

HI @Jasper 

you need to define

• OTP3 = 0x00000001 in order to set QSPI to use non-default GPIOs AFMUX defined in OTPs
• OTP5 and OTP6 : will define the GPIOs settings for each of NCS, CLK, IO0 and IO1. 16-bits for each pin (so OTP7 is not needed). Note that IO2 and IO3 not needed by bootroom (which boot in 1-bit mode), so IO2 and IO3 will be defined in Device Tree together with all QSPI pins.

If you give the non-default pins you require, I can provide to you a set of values for OTPs.
like this (useless) example for:

• PF10-AF9 as CLK
• PB2-AF9 as NCS
• PF8-AF10 as IO0
• PF9-AF10 as IO1

would need:

• OTP3: 0x00000001
• OTP5: 0x22946A97
• OTP6: 0x69A468A4

See also https://wiki.st.com/stm32mpu/wiki/STM32MP13_OTP_mapping#AFmux_configuration

Regards.

[Jasper]

Hi Patrick.

Is there any particular order these signals need to be defined in CFG's?

For example could I start with IO0 then IO1 in CFG5 and then CLK then CS in CF6 or is this not valid?

Also, is it possible to define all 6 non default pins by using CFG7.

The default IO2 and IO3 would be connected to some hardware other than the QSPI device.

I don't know if the ROM code would drive the default IO2 and IO3 to some value during ROM boot.

Thanks.

The non-default pins I'm considering:

PD4 - QUADSPI_CLK, AF9

PE14 - QUADSPI_BK1 _NCS, AF9

PD5 - QUADSPI_BK1_IO0, AF9

PE9 - QUADSPI_BK1 _IO1, AF9

PD11 - QUADSPI_BK1_IO2, AF9

PD15  - QUADSPI_BK1_IO3, AF9

[PatrickF · Accepted solution]

Hi @Jasper 

no order, BootROM blindly apply all OTP5, 6 and 7 content.

It is possible to define whatever you want, up to 6 pins. Anyway, for QSPI Boot point of view only CLK, CMD, IO0 and IO1 are required.

As soon as OTP3 define to use non-default pins for QSPI, BootROM does not map anymore the default pins for CLK, CMD, IO0 and IO1.

IO2 and IO3 would never be set nor used by BootROM, so no risk of any conflict.

Note: some Serial memories can use IO2 and IO3 pins as additional feature such as hold. To
enable such device to boot, it might be necessary to set those pins to inactive level by adding external pull-ups or by defining internal pull-up during Boot using OTP7.

For later boot stage, you need to define your full QSPI pinmux in uBoot Device Tree which will override those used by BootROM.

Regarding you chosen pins, to enable the boot, you would need :

• OTP3: 0x00000001
• OTP5: 0x5E944497
• OTP6: 0x59944594
• OTP7: not used (keep 0x00000000). See above or AN5474 regarding Serial flash 'hold' pin.

Please double check these values according to your need and https://wiki.st.com/stm32mpu/wiki/STM32MP13_OTP_mapping#AFmux_configuration

Regards.