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SPL Initialize Error on DDR Ram speed

gianlucarenzi
Associate III

‎2022-08-04 08:10 AM

Hello,

I am trying to bring up a custom board based on the STM32MP157D MPU via SDCard.

I am using u-boot 2022-01-rc3 as bootloader and the boot is using SPL (I have an SDCard with a GPT Partition table with fsbl1, fsbl2 and ssbl named partitions).

This is the 2nd time I am using this u-boot to bring up a custom STM32MP15x board.

The first time was using a STM32MP151a and I needed to activate the clock tree for the USART1 and modified the low level setup in the stm32mp1_clk source code to enable the USART1 clocks and to activate the serial port #1 to have the SPL ready to print as soon it starts.

But now, something goes wrong. I am using a DDR3 layout as the ED1 evaluation kit as 2x4GB (2x16 bit) 533Mhz DDR RAM. Using the same clk initialization stuff in the ddr3-1066-888-bin-g-2x4gb-533mhz device tree file, and the rcc configuration as follow:

&rcc {
	status = "okay";
	st,clksrc = <
		CLK_MPU_PLL1P
		CLK_AXI_PLL2P
		CLK_MCU_PLL3P
		CLK_PLL12_HSE
		CLK_PLL3_HSE
		CLK_PLL4_HSE
		CLK_RTC_LSE
		CLK_MCO1_DISABLED
		CLK_MCO2_DISABLED
	>;
 
	st,clkdiv = <
		1 /*MPU*/
		0 /*AXI*/
		0 /*MCU*/
		1 /*APB1*/
		1 /*APB2*/
		1 /*APB3*/
		1 /*APB4*/
		2 /*APB5*/
		23 /*RTC*/
		0 /*MCO1*/
		0 /*MCO2*/
	>;
 
	st,pkcs = <
		CLK_CKPER_HSE
		CLK_FMC_ACLK
		CLK_QSPI_ACLK
		CLK_ETH_DISABLED
		CLK_SDMMC12_PLL4P
		CLK_DSI_DSIPLL
		CLK_STGEN_HSE
		CLK_USBPHY_HSE
		CLK_SPI2S1_PLL3Q
		CLK_SPI2S23_PLL3Q
		CLK_SPI45_HSI
		CLK_SPI6_HSI
		CLK_I2C46_HSI
		CLK_SDMMC3_PLL4P
		CLK_USBO_USBPHY
		CLK_ADC_CKPER
		CLK_CEC_LSE
		CLK_I2C12_HSI
		CLK_I2C35_HSI
		CLK_UART1_HSI
		CLK_UART24_HSI
		CLK_UART35_HSI
		CLK_UART6_HSI
		CLK_UART78_HSI
		CLK_SPDIF_PLL4P
		CLK_FDCAN_PLL4R
		CLK_SAI1_PLL3Q
		CLK_SAI2_PLL3Q
		CLK_SAI3_PLL3Q
		CLK_SAI4_PLL3Q
		CLK_RNG1_LSI
		CLK_RNG2_LSI
		CLK_LPTIM1_PCLK1
		CLK_LPTIM23_PCLK3
		CLK_LPTIM45_LSE
	>;
 
	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
	pll2: st,pll@1 {
		compatible = "st,stm32mp1-pll";
		reg = <1>;
		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
		frac = < 0x1400 >;
		u-boot,dm-pre-reloc;
	};
 
	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
	pll3: st,pll@2 {
		compatible = "st,stm32mp1-pll";
		reg = <2>;
		cfg = < 1 33 1 16 36 PQR(1,1,1) >;
		frac = < 0x1a04 >;
		u-boot,dm-pre-reloc;
	};
 
	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
	pll4: st,pll@3 {
		compatible = "st,stm32mp1-pll";
		reg = <3>;
		cfg = < 3 98 5 7 7 PQR(1,1,1) >;
		u-boot,dm-pre-reloc;
	};
};

it fails with:

U-Boot SPL 2022.01-rc3 (Aug 04 2022 - 17:01:02 +0200)
RAM: EK470 DDR3-DDR3L 32bits 533000kHz
stm32mp1_clk rcc@50000000: stm32mp1_clk_disable: id clock 228 has been disabled
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 220 has been enabled
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 222 has been enabled
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 226 has been enabled
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 229 has been enabled
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 224 has been enabled
id=15 clock = 1fc4ef40 : 533000 kHz
stm32mp1_clk rcc@50000000: computed rate for id clock 224 is 533000000 (parent is PLL2_R)
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 228 has been enabled
get_ram_size(c0000000, 40000000)
info.size: 4
DDR invalid size : 0x4, expected 0x40000000
DRAM init failed: -22
### ERROR ### Please RESET the board ###

I suppose the ddr3 setup file in u-boot dts is using the right setup of memory (as the ed1 board I suppose it is working fine), so I cannot understand why the get_ram_size() function returns a single 32 bit (4 bytes) size.

Can help you out to jump over this issue?

Can be a wrong voltage on the DRAM chips?

Regards,

Gianluca

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3 REPLIES 3
gianlucarenzi
Associate III

‎2022-08-04 08:16 AM

as far as I know the vdd_ddr: buck2 is 1350000 microvolts 1.35V in the device-tree configuration of the STPMIC2APQR.

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gianlucarenzi
Associate III

‎2022-08-05 02:25 AM

Just checked. VDD_DDR (despite the Buck2In is present (5VCC)) is 0V. This should explain the wrong DDR Calculation. Maybe it needs a working SDRAM chip ofcourse.

Now the REGULATORS is defined in the config:

CONFIG_PINCONF=y
# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_PINCTRL_STMFX=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_STPMIC1=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_STM32_VREFBUF=y
CONFIG_DM_REGULATOR_STPMIC1=y

as well as the i2c4 setup (pinmux and i2c core) in the device tree:

&pinctrl_z {
	u-boot,dm-pre-reloc;
 
	i2c4_pins_z_mx: i2c4_mx-0 {
		pins {
			pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
					 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
			bias-disable;
			drive-open-drain;
			slew-rate = <0>;
		};
	};
 
	i2c4_sleep_pins_z_mx: i2c4_sleep_mx-0 {
		pins {
			pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
					 <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
		};
	};

The same is applied to the i2c4 bus controller:

&i2c4 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c4_pins_z_mx>;
	pinctrl-1 = <&i2c4_sleep_pins_z_mx>;
	i2c-scl-rising-time-ns = <185>;
	i2c-scl-falling-time-ns = <20>;
	clock-frequency = <100000>;
	status = "okay";
	/* spare dmas for other usage */
	/delete-property/dmas;
	/delete-property/dma-names;
 
	pmic: stpmic@33 {
		compatible = "st,stpmic1";
		reg = <0x33>;
		interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;
		status = "okay";
 
		regulators {
			compatible = "st,stpmic1-regulators";
			buck1-supply = <&vin>;
			buck2-supply = <&vin>;
			buck3-supply = <&vin>;
			buck4-supply = <&vin>;
			ldo1-supply = <&v3v3>;
			ldo2-supply = <&vin>;
			ldo3-supply = <&vdd_ddr>;
			ldo4-supply = <&vin>;
			ldo5-supply = <&vin>;
			ldo6-supply = <&v3v3>;
			vref_ddr-supply = <&vin>;
			boost-supply = <&vin>;
			pwr_sw1-supply = <&bst_out>;
			pwr_sw2-supply = <&bst_out>;
 
			vddcore: buck1 {
				regulator-name = "vddcore";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1350000>;
				regulator-always-on;
				regulator-initial-mode = <0>;
				regulator-over-current-protection;
			};
 
			vdd_ddr: buck2 {
				regulator-name = "vdd_ddr";
				regulator-min-microvolt = <1350000>;
				regulator-max-microvolt = <1350000>;
				regulator-always-on;
				regulator-initial-mode = <0>;
				regulator-over-current-protection;
			};
 
			vdd: buck3 {
				regulator-name = "vdd";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
				st,mask-reset;
				regulator-initial-mode = <0>;
				regulator-over-current-protection;
			};
 
			v3v3: buck4 {
				regulator-name = "v3v3";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
				regulator-over-current-protection;
				regulator-initial-mode = <0>;
			};
 
			vtt_ddr: ldo3 {
				regulator-name = "vtt_ddr";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-over-current-protection;
			};
 
			vdd_usb: ldo4 {
				regulator-name = "vdd_usb";
				interrupts = <IT_CURLIM_LDO4 0>;
			};
 
			vdda: ldo5 {
				regulator-name = "vdda";
				regulator-min-microvolt = <2900000>;
				regulator-max-microvolt = <2900000>;
				interrupts = <IT_CURLIM_LDO5 0>;
				regulator-boot-on;
			};
 
			vref_ddr: vref_ddr {
				regulator-name = "vref_ddr";
				regulator-always-on;
			};
 
			 bst_out: boost {
				regulator-name = "bst_out";
				interrupts = <IT_OCP_BOOST 0>;
			 };
 
			vbus_otg: pwr_sw1 {
				regulator-name = "vbus_otg";
				interrupts = <IT_OCP_OTG 0>;
			 };
 
			 vbus_sw: pwr_sw2 {
				regulator-name = "vbus_sw";
				interrupts = <IT_OCP_SWOUT 0>;
				regulator-active-discharge = <1>;
			 };
		};
 
		watchdog {
			compatible = "st,stpmic1-wdt";
			status = "disabled";
		};
	};
};

And, of course, the &i2c4 used in SPL and is enabled with: &i2c4{ u-boot,dm-pre-reloc; status="okay"; } as well as the &pinctrl_z { u-boot,dm-pre-reloc; status = "okay"; }

Even the pmic node is enabled in the SPL section with: &pmic { u-boot,dm-pre-reloc; status = "okay"; }

Is there a way to check (easely) with a scope, if the SPL is using the spl pmic driver *BEFORE* checking the RAM controller. It should be called as soon as possible during boot-up.

Do you agree with me?

Regards,

Gianluca

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Olivier GALLIEN
ST Employee

‎2022-09-14 05:21 AM

Hi @gianlucarenzi​ ,

I read :

"u-boot 2022-01-rc3 as bootloader and the boot is using SPL"

Likely Vanilla U-boot version not yet integrated and ST no more support SPL for MP1.

I recommend you to use an OpenSTLinux delivery to get better support.

STM32 MPU OpenSTLinux release note - v4.0.0 - stm32mpu

Olivier

Olivier GALLIEN
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