Dear ST Rep,
The information within AN5489 regarding the pin-lengths for the high-speed serial interfaces of the MP2 (ie,. DSI / CSI / LVDS / and "COMBOPHY") potentially has some errors, or at the very least is unclear and I would greatly appreciate some help making sense of it.
Side note - The raw pin-length data provided for the DDR interface is exactly what a designer wants/needs in a design. I'm not sure why the same information for the other high-speed interfaces on the MP2 was converted as it was, but it's far less useful (imho). If the raw pin length data could be provided for the above-mentioned interfaces - all my questions will be answered.
To that end - I struggle to make sense of the information regarding the trace length matching for high-speed interfaces (via AN5489), for the reasons stated below:
- Per Section 8.19: (pg. 78; Rev3)
- "Each package has been optimized to provide easier length matching when differential balls pair signals are not
- directly on adjacent balls. Example: package with 0.8 mm ball pitch, when differential pairs are on two different
- rows, the package already have around 800 μm length internal difference to allow the PCB track to match total
- length with minimum or even no additional routing complexity. Following table shows (for example, xN minus xP)
- length difference (inside package) at ball level to be taken into account by the PCB tool."
- Per Figure 47 one sees that: (pg 78; Rev3)
- The Grey Diff. Traces come from pads at the same row, therefore the PCB routed traces will already be equal and no additional tuning is required.
- Conclusion - GOOD, this agrees with the statements in Section 8.19.
- The Green Diff. Traces have the "xN" pad on the inside row and the "xP" pad on the outside row. Thus, as the arrow indicates (and Section 8.19 states) "xN minus xP" = -800um (ie, pin length on the outside pad is longer than that of the inside pad, mitigating the length tuning needed on the PCB).
- Conclusion - GOOD, this agrees with the statements in Section 8.19.
- The Orange Diff. Traces have the "xP" pad on the inside row and the "xN" pad on the outside row. Thus, as the arrow indicates (and Section 8.19 states) "xN minus xP" = 1131um (ie, pin length on the outside pad is longer than that of the inside pad, mitigating the length tuning needed on the PCB).
- Conclusion - GOOD, this agrees with the statements in Section 8.19.
- The Blue Diff. Traces have the "xP" pad on the inside row and the "xN" pad on the outside row. Thus, based on the arrow (and Section 8.19 statements) "xN minus xP" should equal 800um (ie, pin length on xN is greater than that on xP, to mitigate length tuning on the PCB), but Fig. 47 shows this difference as being (-)800um.
- Conclusion - This is the exact opposite of the statements in Section 8.19, this exacerbates the length tuning required on the PCB.
- I'm guessing that the (-) sign is an error, and that the value should be (+) 800um (ie,. xN has a longer pin length than xP). Yes - ?
- OR - Should the arrow be pointing the other direction (xP minus xN); and really it's the shorter pin length that's always subtracted from the longer pin-length? If this is true, then the orange diff traces appear to be in the reverse order too, but somehow still got the correct pin-length of xN minus xP.
- Reference image of Figure 47:
If the (-) sign on the Blue Diff. Traces is simply a typo, and the logic is simply "xN minus xP = difference length", then everything above makes sense. However, if we do so, and then apply said logic to the very next item in the app note "Table 25. Package length matching values", we find the following errors/discrepancies with the statements in Section 8.19 (Each package has been optimized to provide easier length matching when differential balls pair signals are not directly on adjacent balls).
Pin Name | Pad/Ball | Length Delta | Conclusion / Notes: |
DSI Interface: | |||
DSI_CKP | B4 | 207 | Therefor: Pin length of A4 (the Outer pin) is 207um longer than B4s (the Inner pin) |
DSI_CKN | A4 | Conclusion: This agrees with the statements in Section 8.19. | |
DSI_D0P | B5 | 57 | Therefor: Pin length of A5 (the Outer pin) is 57um longer than B5s (the Inner pin) |
DSI_D0N | A5 | Conclusion: This agrees with the statements in Section 8.19. | |
DSI_D1P | B6 | -366 | Therefor: Pin length of A6 (the Outer pin) is 366um Shorter than B5s (the Inner pin) |
DSI_D1N | A6 | Conclusion: This is worse for PCB length tuning and Contrasts with the statements in Section 8.19. | |
* There are no information, regarding the length tuning for DSI Diff Pairs: DSI_2P/N & DSI_3P/N. Is this missing? | |||
Pin Name | Pad/Ball | Length Delta | Conclusion / Notes: |
CSI Interface: | |||
CSI_CKP | C1 | 147 | Therefor: Pin length of C1 (the Outer pin) is 147um Shorter than C2s (the Inner pin). |
CSI_CKN | C2 | Conclusion: This is worse for PCB length tuning and Contrasts with the statements in Section 8.19. | |
CSI_D0P | E2 | -450 | Therefor: Pin length of E1 (the Outer pin) is 450um Shorter than E2s (the Inner pin). |
CSI_D0N | E1 | Conclusion: This is worse for PCB length tuning and Contrasts with the statements in Section 8.19. | |
CSI_D1P | D1 | 162 | Therefor: Pin length of D1 (the Outer pin) is 162um Shorter than D2s (the Inner pin). |
CSI_D1N | D2 | Conclusion: This is worse for PCB length tuning and Contrasts with the statements in Section 8.19. | |
Pin Name | Pad/Ball | Length Delta | Conclusion / Notes: |
USB Interface: | |||
USBH_HS_DP | W11 | -11 | Therefor: Pin length of W11 (the Outer pin) is 11um longer than V11s (the Inner pin). |
USBH_HS_DM | V11 | Conclusion: This agrees with the statements in Section 8.19. | |
USB3DR_DP | W12 | 27 | Therefor: Pin length of W12 (the Outer pin) is 27um Shorter than V12s (the Inner pin). |
USB3DR_DM | V12 | Conclusion: This is worse for PCB length tuning and Contrasts with the statements in Section 8.19. | |
Pin Name | Pad/Ball | Length Delta | Conclusion / Notes: |
COMBOPHY Interface: | |||
COMBOPHY_TX1P | U15 | 336 | Therefor: Pin length of V15 (the Outer pin) is 336um longer than U15s (the Inner pin). |
COMBOPHY_TX1N | V15 | Conclusion: This agrees with the statements in Section 8.19. | |
COMBOPHY_RX1P | U16 | -191 | Therefor: Pin length of V16 (the Outer pin) is 191um Shorter than U16s (the Inner pin). |
COMBOPHY_RX1N | V16 | Conclusion: This is worse for PCB length tuning and Contrasts with the statements in Section 8.19. | |
*Note: LVDS interface not included for brevity…* |
Given how many conflicts there are within Table 25, I have to assume that the length deltas are not simply "xN minus xP". That said, if the length delta was instead a measure in favor of the expected PCB trace length matching, I don't understand why there are both positive and negative values.(?)
Seeing that the routing guidelines for many of these signals is to maintain +/- 5mils, wrongly interpreting the above information will quickly put the routing out of tolerance and potentially nonfunctional.
Apologies for my ignorance here but any assistance or clarification as to how to correctly implement trace length matching for these interfaces would be greatly appreciated. :)
Thank you for you time and efforts and have a great day.
~ Jay
~ Jay
