cancel
Showing results for 
Search instead for 
Did you mean: 

ksz8041 bring up

MWoło.2
Senior II

It seems that I have a problem with DMA, but I'm not sure. Would you please take a look at the below screen

0693W00000FDX7aQAH.pngDts looks

0693W00000FDX7zQAH.jpg0693W00000FDX84QAH.jpgI intend to achieve MII with self-generated quartz.

Unfortunately, I'm stuck on this "Failed to reset the DMA".

22 REPLIES 22
OlivierK
ST Employee

Hi MWoło.2 (Community Member)

What is the value of the SYSCFG_PMCSETR register one you've booted up the kernel?

> devmem2 0x50000A10 W 0x00000800

> devmem2 0x50020004 W

Regards

MWoło.2
Senior II
root@stm32mp157a-visionsom-dsi-sd-mx:~# devmem2 0x50000A10 W 0x00000800         
/dev/mem opened.                                                                
Memory mapped at address 0xb6f4e000.                                            
Read at address  0x50000A10 (0xb6f4ea10): 0x00000000                            
Write at address 0x50000A10 (0xb6f4ea10): 0x00000800, readback 0x00000800       
root@stm32mp157a-visionsom-dsi-sd-mx:~# devmem2 0x50020004 W                    
/dev/mem opened.                                                                
Memory mapped at address 0xb6fb1000.                                            
Read at address  0x50020004 (0xb6fb1004): 0x00100000                            
root@stm32mp157a-visionsom-dsi-sd-mx:~# 

MWoło.2
Senior II
root@stm32mp157a-visionsom-dsi-sd-mx:~# devmem2 0x50000A10 W 0x00000800         
/dev/mem opened.                                                                
Memory mapped at address 0xb6f4e000.                                            
Read at address  0x50000A10 (0xb6f4ea10): 0x00000000                            
Write at address 0x50000A10 (0xb6f4ea10): 0x00000800, readback 0x00000800       
root@stm32mp157a-visionsom-dsi-sd-mx:~# devmem2 0x50020004 W                    
/dev/mem opened.                                                                
Memory mapped at address 0xb6fb1000.                                            
Read at address  0x50020004 (0xb6fb1004): 0x00100000                            
root@stm32mp157a-visionsom-dsi-sd-mx:~#

OlivierK
ST Employee

Hi MWoło.2  (Community Member),

That is the correct value according to your setup: MII with external oscillator/crystal. The applied clocks settings in the DT seems correct.

Have you checked the external PHY h/w connections: VDD supply, PHY boot strapping, reset signal?

What about a dhcp test in U-boot?

Rgds,

Olivier

MWoło.2
Senior II

Do I need connect reset to pin GPIO pin?

MWoło.2
Senior II

Regarding hardware, I found a few mistakes. Please take a look at it

https://github.com/voloviq/stm32mp1-custom-devboard/issues

maybe these issues can be a real problem. I rework the circuit and keep you informed.

PatrickF
ST Employee

Hi,

please check on your board that the PHY is providing a clock on ETH_TX_CLK pin (output from PHY in MII mode) during initialization. Missing this clock is usually the root cause of 'failed to reset the dma' message.

If no clock, please check carefully PHY connections and PHY HW config pins.

Regards.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.
OlivierK
ST Employee

Hi,

It's good common practice to connect the PHY reset input to a GPIO, here PA4 is used.

phy0: ethernet-phy@0 {

reset-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>

reset-assert-us = <1000>;

reset-deassert-us = <2000>;

reg = <0>;

};

Rgds,

OlivierK
ST Employee

One more thing, there are different Micrel properties applied depending of the Mickel 8041 chosen part, it may be important to add the right part version in the DT:

phy0: ethernet-phy@0 {

compatible = "ethernet-phy-id0007.c131";

reset-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>

reset-assert-us = <1000>;

reset-deassert-us = <2000>;

reg = <0>;

};

You need to find and replace value 0007.c131 corresponding to your Ethernet PHY: this can be found in datasheet of the Ethernet PHY, and find PHY Identifier 1 and PHY Identifier 2 registers.

MWoło.1
Associate II

OK, I check it and go back with feedback.

Thanks a lot for the hints.

BR Michal