How to write STM32MP153 registers (RCC_RDLSICR)?

[SScar.2]

Hi, 

I'm trying to change the value of the register RCC_RDLSICR (RCC reset duration and LSI control register, address offset 0x144). I need to change the Minimum Reset Duration value.

In all power management/low power handling manuals for STM32MP15x lines the documentation says that you can change the registers value, but I can't find HOW I can achieve that. 

I can write them in dts? inside u-boot? please I need clarifications about that. 

NOTE: I'm using a custom STM32MP153 board with OpenSTLinux distribution on it. 

Thanks a lot

[PatrickF]

Hi @SScar.2 

I think you have to adapt TF-A code.

I found some lines related to non-STPMIC case which modify this register.

https://github.com/STMicroelectronics/arm-trusted-firmware/blob/v2.8-stm32mp/plat/st/stm32mp1/bl2_plat_setup.c#L291

Regards,

[SScar.2]

Hi Patrick, 

thanks for the quick response! 

Our solution adopts STPMIC. I don't know if this is useful information... 

I could patch the TF-A, but please specify which file I should modify. I'm pretty new to tf-a and I never patched it.

Thanks again

[SScar.2 · Accepted solution]

Got IT!! 

---
 plat/st/stm32mp1/bl2_plat_setup.c | 10 +++++++---
 plat/st/stm32mp1/stm32mp1_ssp.c   | 10 +++++++---
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 6232d7b..795cefe 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -286,10 +286,14 @@ void bl2_el3_plat_arch_setup(void)
 	}
 
 	/* Set minimum reset pulse duration to 31ms for discrete power supplied boards */
-	if (dt_pmic_status() <= 0) {
-		mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, RCC_RDLSICR_MRD_MASK,
+	// if (dt_pmic_status() <= 0) {
+	// 	mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, RCC_RDLSICR_MRD_MASK,
+	// 			   31U << RCC_RDLSICR_MRD_SHIFT);
+	// }
+
+	//SS set minimum reset pulse duration MDR register to 31 ms for ALL configurations 
+	mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, RCC_RDLSICR_MRD_MASK,
 				   31U << RCC_RDLSICR_MRD_SHIFT);
-	}
 
 	generic_delay_timer_init();
 
diff --git a/plat/st/stm32mp1/stm32mp1_ssp.c b/plat/st/stm32mp1/stm32mp1_ssp.c
index 14ce023..9900672 100644
--- a/plat/st/stm32mp1/stm32mp1_ssp.c
+++ b/plat/st/stm32mp1/stm32mp1_ssp.c
@@ -927,10 +927,14 @@ void bl2_el3_plat_arch_setup(void)
 	}
 
 	/* Set minimum reset pulse duration to 31ms for discrete power supplied boards */
-	if (dt_pmic_status() <= 0) {
-		mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, RCC_RDLSICR_MRD_MASK,
+	// if (dt_pmic_status() <= 0) {
+	// 	mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, RCC_RDLSICR_MRD_MASK,
+	// 			   31U << RCC_RDLSICR_MRD_SHIFT);
+	// }
+
+	//SS set minimum reset pulse duration MDR register to 31 ms for ALL configurations 
+	mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, RCC_RDLSICR_MRD_MASK,
 				   31U << RCC_RDLSICR_MRD_SHIFT);
-	}
 
 	generic_delay_timer_init();
 
-- 
2.25.1

 I patched both bl2_plat_setup.c and stm32mp1_ssp.c and it works (yes, I bypassed the check of the pmic status/mode), now when I reset the board I can see 31ms on the signal. 

[PatrickF]

Hi,

as you are using STPMIC1, may I ask you the rationale to extend the NRST duration to 31ms ?

Could help other too.

Regards.

[SScar.2]

Hi @PatrickF , 

that's an excellent question... actually, I don't know. I saw that our custom board, which has a particular power logic (by the way, if you could ping your colleagues about my other threads, that would be great :) ),  

couldn't handle a proper reboot. We saw that the NRST impulse was 20us and It wasn't enough to restart the board properly. It's our first embedded Linux board, so we're surely doing something wrong. Also, I'm not using the latest OpenSTLinux ecosystem, so maybe some software bug is going on too. Still, with this patch, the board seems to reboot properly. 

It would be great if you could enlighten us about what's going on! 

Thanks 

[PatrickF]

Hi,

20us is enough for STPMIC1 to detect it's RSTn input and start a power off/on sequence, so NRST will be tied low by STPMIC1 for few tens of ms (and thanks to the mandatory 10nF on NRST, the initial 20us from STM32MP1 will be extended to slightly more time in reality).

For other posts, I don't know all your HW details and requirements, but usually you could use BUCK3 (VDD) to maintain a 'system' main SMPS (e.g. from 48V to 5V) as VDD is kept high during all power modes including reset sequence (thanks to some SW setting in STPMIC1), except when platform shutdown is requested to STPMIC1 (then VDD is going low).

STM1601 could sometimes be used if suitable for your needs (using a GPIO or VDD as 'processor control')

Regards.

[SScar.2]

Hi @PatrickF , 

you were right. A hardware problem on the board prevented the RSTn signal from moving properly. 

Btw, let's let a trace of the tf-a patch in this thread, there are not many examples on the internet. 

Cheers