2021-08-02 08:09 AM
Hello,
I am having difficulties with the MMC bus and the external SDIO wifi module. We are using the wifi module jody-w263 from U-blox with the OSD32MP1, and the communication with the module works, but it is quite slow. The wifi module is capable of SDR 104 and DDR50 communication speeds, but I add the support to the DTS, the communication is broken and the device returns the -110 while initializing.
How can I add support for higher speeds?
I attach the working dts, dmesg, ios and caps, and relevant schematic.
Any suggestion will be appreciated.
Best regards,
Tomáš.
Solved! Go to Solution.
2021-09-29 10:59 PM
I have tried your suggestion but the wlan still uses the sd high-speed timing spec.
The sdmmc3 node looks like this:
&sdmmc3{
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc3_pins_mx>;
pinctrl-1 = <&sdmmc3_opendrain_pins_mx>;
pinctrl-2 = <&sdmmc3_sleep_pins_mx>;
status = "okay";
/* USER CODE BEGIN sdmmc3 */
arm,primecell-periphid = <0x10153180>;
non-removable;
no-sd;
no-mmc;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
/*vqmmc-supply = <&v1v8_ldo1>;*/
mmc-pwrseq = <&wifi_pwrseq>;
/* USER CODE END sdmmc3 */
};
and the /sys/kernel/debug/mmc0/ios:
clock: 50000000 Hz
actual clock: 34812988 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 2 (4 bits)
timing spec: 2 (sd high-speed)
signal voltage: 0 (3.30 V)
driver type: 0 (driver type B)
2021-09-29 11:39 PM
Ok. something I miss here. Let me check with experts and I'll come back to you.
2021-09-30 12:25 AM
Signal voltage is not correct in sysfs (3,3v instead of 1,8v). Was it better with "vqmmc-supply = <&v1v8_ldo1>;" property ?
2021-09-30 01:01 AM
No, the signal voltage was 3v3.
2021-09-30 02:38 AM
I/ For us the right config is this one (but you already said it was not working):
sd-uhs-ddr50;
vmmc-supply = <&v3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
Now the Wlan chip and the stm32mp1 should negotiate the interface speed and maybe something is going wrong ...
Could you please with this config activate the traces in sdmmc ? (ie: root:~# echo "file drivers/mmc/* +p" > /sys/kernel/debug/dynamic_debug/control).
II/ We have seen one issue on your clock (not related to above issue):
clock: 50000000 Hz
actual clock: 34812988 Hz
Make sure your clock tree generate a clock close to 50MHz to get better performance (like for EMMC).
I assume you are on the lastest release (5.10 kernel).
2021-09-30 03:45 AM
I) I attached the dmesg output after enabling the debug and rebinding the driver.
II) We changed the peripheral clock setup so now the SDMMC3 uses the 200 MHz. This is divided by driver to the 50Mhz.
cat /sys/kernel/debug/mmc0/ios
clock: 50000000 Hz
actual clock: 50000000 Hz
The kernel we use is 5.4.56 because the WLAN driver supports only kernels up to 5.5. Could this be related to the kernel version? I think we could use an open-source version of the driver in the 5.10 kernel release.
2021-09-30 06:07 AM
for uhs, the driver will need to process on rising and falling edge of the data clock. So the driver needs at least 2x the io clock.
2021-09-30 06:09 AM
We don't see much more information in the trace unfortunately. There is a timeout at start so no communication with the external chip.
2021-09-30 06:46 AM
Considering you already tested before in high speed @50 MHZ and you had the same timeout.
Do you have the possibility to look at your IOs ? Do you have the right 1,8v and some data exchanged with the wlan ?
2021-09-30 09:24 AM
I am not sure what you mean now. We can communicate with the WLAN module (in HS mode at 50MHz) but the communication is slow (approx. 1.5~2 MB/s), this could be some timeout issue, but the PatrickF tested the speed with the MURATA module and got similar results. And as I said before, we tried this WLAN with a CPU module from NXP and the speed was around 4.5 MB/s even if the SDIO speed was limited to 22 MHz.
I attach images and data export from the oscilloscope. The signals are:
The images are taken with different timebase for better readability.