2023-11-20 05:21 PM
We are using Murata LBEE5HY1MW WiFi/BT module with a STM32MP157F based custom board, running OSD32MP1 Debian SDK v3.0 (Linux Kernel v5.10-stm32mp)
LBEE5HY1MW module is connected to STM32MP157F via sdmmc3 (WiFi) and usart2 (Bluetooth) interface.
Due to some limitations, we have to set the IO voltage to 3.3V (we can not use 1.8V on board).
We are not getting the recommended throughput when we run WiFi throughput tests via iperf3.
On average we got ...
We tried different configurations but the WiFi throughput does not go beyond 54Mbps.
The command wl status returns that the supported rate is 54Mbps at most.
We tried changing the sdio bus speed parameter in device tree to different values (SDR104, SDR50, DDR50), but it has no effect, sdio bus speed remains fixed at 49.5 MHz and DDR52. Not sure if this is due to 3.3v supply.
Below are some of the commands showing wifi status followed by Kernel device-tree excerpt
Any help or suggestion to enable 802.11ac with a higher throughput is much appreciated.
Thanks.
/Farid
$ dmesg | grep brcm
[ 24.080346] brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac43455-sdio for chip BCM4345/6
[ 24.371384] brcmfmac: brcmf_c_preinit_dcmds: Firmware: BCM4345/6 wl0: Aug 29 2023 01:47:08 version 7.45.265 (28bca26 CY) FWID 01-b677b91b
[ 25.941805] Bluetooth: hci0: BCM4345C0 'brcm/BCM4345C0.hcd' Patch
$ iw dev wlan0 link
Connected to 72:72:cb:1c:5c:5c (on wlan0)
SSID: Hamed’s iPhone
freq: 5745
RX: 4096 bytes (29 packets)
TX: 2868 bytes (29 packets)
signal: -53 dBm
rx bitrate: 433.3 MBit/s
tx bitrate: 433.3 MBit/s
bss flags:
dtim period: 3
beacon int: 100
$ wl status
SSID: “Hamed’s iPhone”
Mode: Managed RSSI: -49 dBm SNR: 0 dB noise: -91 dBm Flags: RSSI on-channel Channel: 149/80
BSSID: 72:72:CB:1C:5C:5C Capability: ESS WEP RRM
Supported Rates: [ 6(b) 9 12(b) 18 24(b) 36 48 54 ]
RSN:
multicast cipher: AES-CCMP
unicast ciphers(1): AES-CCMP
AKM Suites(2): WPA2-PSK WPA3
Capabilities(0x008c):
No Pre-Auth
Pairwise
MFP not Required
MFP Capable
16 PTK Replay Ctrs
1 GTK Replay Ctr
Extended Capabilities:
VHT Capable:
Chanspec: 5GHz channel 155 80MHz (0xe09b)
Primary channel: 149
HT Capabilities: 40Mhz SGI20 SGI40
Supported HT MCS : 0-7
Supported VHT MCS:
NSS1 Tx: 0-9 Rx: 0-9
NSS2 Tx: 0-9 Rx: 0-9
VS_IE:dd0a0017f206010103010000
VS_IE:dd0f0017f2060301080000006233617374
VS_IE:dd0500904c0407
VS_IE:dd0a0010180200001c000002
VS_IE:dd180050f2020101800003a4000027a4000042435e0062322f00
eMMC @ SDMMC2
$ cat /sys/kernel/debug/mmc0/ios
clock: 50000000 Hz
actual clock: 49500000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 2 (4 bits)
timing spec: 2 (sd high-speed)
signal voltage: 0 (3.30 V)
driver type: 0 (driver type B)
WiFi module @ SDMMC3
$ cat /sys/kernel/debug/mmc1/ios
clock: 52000000 Hz
actual clock: 49500000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 3 (8 bits)
timing spec: 8 (mmc DDR52) => setting sd-uhs-sdr104 in device tree has no effect
signal voltage: 0 (3.30 V)
driver type: 0 (driver type B)
/* MicroSD */
&sdmmc1{
status = "disabled";
};
/* eMMC */
&sdmmc2{
u-boot,dm-pre-reloc;
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_pins_mx>;
pinctrl-1 = <&sdmmc2_opendrain_pins_mx>;
pinctrl-2 = <&sdmmc2_sleep_pins_mx>;
status = "okay";
non-removable;
no-sd;
no-sdio;
st,neg-edge;
bus-width = <8>;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&v3v3>;
mmc-ddr-3_3v;
};
/* WiFi */
&sdmmc3{
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc3_pins_mx>;
pinctrl-1 = <&sdmmc3_opendrain_pins_mx>;
pinctrl-2 = <&sdmmc3_sleep_pins_mx>;
arm,primecell-periphid = <0x10153180>;
non-removable;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
#address-cells = <1>;
#size-cells = <0>;
sd-uhs-sdr104;
keep-power-in-suspend;
status = "okay";
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* Bluetooth */
&usart2{
pinctrl-names = "default", "sleep";
pinctrl-0 = <&usart2_pins_mx>;
pinctrl-1 = <&usart2_sleep_pins_mx>;
uart-has-rtscts;
status = "okay";
bluetooth {
shutdown-gpios = <&gpioe 10 GPIO_ACTIVE_HIGH>;
compatible = "brcm,bcm4345c5";
max-speed = <3000000>;
vbat-supply = <&v3v3>;
vddio-supply = <&v3v3>;
};
};
&pinctrl {
sdmmc3_pins_mx: sdmmc3_mx-0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
<STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
<STM32_PINMUX('F', 1, AF9)>, /* SDMMC3_CMD */
<STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
<STM32_PINMUX('F', 5, AF9)>; /* SDMMC3_D2 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
sdmmc3_opendrain_pins_mx: sdmmc3_opendrain_mx-0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
<STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
<STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
<STM32_PINMUX('F', 5, AF9)>; /* SDMMC3_D2 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
bias-disable;
drive-open-drain;
slew-rate = <1>;
};
pins3 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
sdmmc3_sleep_pins_mx: sdmmc3_sleep_mx-0 {
u-boot,dm-pre-reloc;
pins {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
<STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
<STM32_PINMUX('F', 1, ANALOG)>, /* SDMMC3_CMD */
<STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
<STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
<STM32_PINMUX('G', 15, ANALOG)>; /* SDMMC3_CK */
};
};
usart2_pins_mx: usart2_mx-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 15, AF7)>, /* USART2_CTS */
<STM32_PINMUX('A', 3, AF7)>; /* USART2_RX */
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('A', 1, AF7)>, /* USART2_RTS */
<STM32_PINMUX('A', 2, AF7)>; /* USART2_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
};
usart2_sleep_pins_mx: usart2_sleep_mx-0 {
pins {
pinmux = <STM32_PINMUX('E', 15, ANALOG)>, /* USART2_CTS */
<STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS*/
<STM32_PINMUX('A', 2, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('A', 3, ANALOG)>; /* USART2_RX */
};
};
2023-11-20 11:34 PM
Hello @farid ,
You are based on OpenSTLinux v3 (with kernel 5.10). Note that since OSTL v 4.1.1 (https://wiki.st.com/stm32mpu-ecosystem-v4/wiki/STM32_MPU_OpenSTLinux_release_note_-_v4.1.0#v4-1-1), different things were added to improve WLAN performances, more particularly 2 things :
- SDIO in-band interrupt support
- Out of Band interrupt configuration in our default device tree of stm32mp157f-dk2 (stm32mp157f-dk2.dts)
If I remember well, by default the configuration of the WLAN Murrata chip is configured as In Band interrupt, but the driver was not already ready for that in kernel 5.10. You can try to backport the modifications in your kernel release.
Kind regards,
Erwan.